42 	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
44 	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
81 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));  in tegra_plane_writel()
111 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
112 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
868 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);  in tegra_cursor_atomic_update()
872 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);  in tegra_cursor_atomic_update()
878 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
887 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
891 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);  in tegra_cursor_atomic_update()
908 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
1459 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1468 	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1559 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
1571 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1596 		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);  in tegra_dc_set_timings()
1599 		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);  in tegra_dc_set_timings()
1604 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);  in tegra_dc_set_timings()
1608 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);  in tegra_dc_set_timings()
1612 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);  in tegra_dc_set_timings()
1615 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);  in tegra_dc_set_timings()
1681 		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);  in tegra_dc_commit_state()
1697 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1762 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_disable()
1800 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);  in tegra_crtc_atomic_enable()
1803 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);  in tegra_crtc_atomic_enable()
1809 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
1816 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
1820 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
1823 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
1825 		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_crtc_atomic_enable()
1829 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
1833 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
1838 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);  in tegra_crtc_atomic_enable()
1842 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);  in tegra_crtc_atomic_enable()
1846 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
1850 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
1854 		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);  in tegra_crtc_atomic_enable()
1856 		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);  in tegra_crtc_atomic_enable()
1868 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_atomic_enable()
1874 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_atomic_enable()
1880 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_enable()
1886 		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);  in tegra_crtc_atomic_enable()
1921 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
1925 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
1942 	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);  in tegra_dc_irq()