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Searched refs:phy_write (Results 1 – 25 of 80) sorted by relevance

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/Linux-v4.19/drivers/net/phy/
Dvitesse.c103 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
112 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
138 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
140 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
154 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
156 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
157 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
160 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
161 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
163 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
Dnational.c61 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
67 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
68 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
76 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
79 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
92 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
101 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
104 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
105 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
106 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
[all …]
Dat803x.c89 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
110 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
141 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
142 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
143 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
144 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
145 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
146 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
172 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL, in at803x_set_wol()
174 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA, in at803x_set_wol()
[all …]
Dbcm7xxx.c93 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm7xxx_28nm_b0_afe_config_init()
144 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
172 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
296 ret = phy_write(dev, location, v); in phy_set_clr_bits()
314 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
319 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
329 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
385 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
389 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
395 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
Dmscc.c130 rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_page_set()
151 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
185 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
199 rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val); in vsc85xx_mdix_set()
254 rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val); in vsc85xx_downshift_set()
284 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
285 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
286 phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
288 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
289 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
[all …]
Dmeson-gxl.c65 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
68 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
71 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
74 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
79 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
91 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
115 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
119 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
226 return phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
Dbcm-phy-lib.c29 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_write_exp()
33 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
41 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
48 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0); in bcm_phy_read_exp()
59 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
67 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
77 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
84 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
101 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
108 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
[all …]
Drockchip.c52 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
56 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
60 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
66 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
81 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
84 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
103 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
179 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
Drealtek.c101 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
104 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
114 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
117 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
146 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
147 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
149 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
150 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
184 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
191 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
Ddp83tc811.c213 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
228 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
240 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
243 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
264 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
269 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
289 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
292 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
Ddavicom.c80 temp = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
109 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
126 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
131 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
137 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
Dcicada.c72 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
78 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
96 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
99 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
Dlxt.c84 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
86 return phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
91 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
108 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
110 return phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
239 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
Dmicrochip.c52 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
54 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
58 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
255 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
307 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
311 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
Dbcm-cygnus.c29 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
59 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); in bcm_cygnus_afe_config()
89 rc = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_cygnus_config_init()
97 rc = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm_cygnus_config_init()
Dmicrel.c138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); in kszphy_extended_write()
139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
175 phy_write(phydev, MII_KSZPHY_CTRL, temp); in kszphy_config_intr()
183 return phy_write(phydev, MII_KSZPHY_INTCS, temp); in kszphy_config_intr()
199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); in kszphy_rmii_clk_sel()
225 rc = phy_write(phydev, reg, temp); in kszphy_setup_led()
244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); in kszphy_broadcast_disable()
263 ret = phy_write(phydev, MII_KSZPHY_OMSO, in kszphy_nand_tree_disable()
447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); in ksz9031_extended_write()
[all …]
Dicplus.c112 bmcr = phy_write(phydev, MII_BMCR, bmcr); in ip1xx_reset()
138 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); in ip1001_config_init()
157 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); in ip1001_config_init()
174 c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT); in ip101a_g_config_init()
182 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); in ip101a_g_config_init()
Dqsemi.c76 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
105 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
108 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
Dbcm63xx.c37 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
51 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
60 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
/Linux-v4.19/arch/arm/mach-imx/
Dmach-imx7d.c25 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
26 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
29 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
30 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
31 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
34 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
37 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
40 phy_write(dev, 0x1e, val); in ar8031_phy_fixup()
48 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
49 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
[all …]
Dmach-imx6q.c47 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
49 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
52 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
54 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
55 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
64 phy_write(dev, 0x0d, device); in mmd_write_reg()
65 phy_write(dev, 0x0e, reg); in mmd_write_reg()
66 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
67 phy_write(dev, 0x0e, val); in mmd_write_reg()
116 phy_write(dev, 0xd, 0x7); in ar8031_phy_fixup()
[all …]
Dmach-imx6ul.c37 phy_write(dev, 0x1f, 0x8110); in ksz8081_phy_fixup()
38 phy_write(dev, 0x16, 0x201); in ksz8081_phy_fixup()
40 phy_write(dev, 0x1f, 0x8190); in ksz8081_phy_fixup()
41 phy_write(dev, 0x16, 0x202); in ksz8081_phy_fixup()
Dmach-imx6sx.c26 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
27 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
30 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
33 phy_write(dev, 0x1e, val); in ar8031_phy_fixup()
/Linux-v4.19/drivers/net/ethernet/ibm/emac/
Dphy.c32 #define phy_write _phy_write macro
62 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
73 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
125 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
145 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
157 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
163 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
183 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
200 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
330 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/Linux-v4.19/arch/powerpc/platforms/85xx/
Dmpc85xx_mds.c81 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
86 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
96 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
107 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
118 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
123 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
140 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
152 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()

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