103 	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);  in vsc824x_add_skew()
112 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc824x_config_init()
138 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
140 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
154 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
156 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
157 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
160 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
161 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
163 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
171 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
173 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
174 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
175 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
176 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
177 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
178 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
179 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
180 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
181 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
183 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
184 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
187 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
188 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
191 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
192 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
193 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
194 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
196 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
202 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
204 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
219 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
221 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
222 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
225 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
226 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
228 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
230 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
231 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
232 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
235 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
237 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
266 	return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);  in vsc8601_add_skew()
301 		err = phy_write(phydev, MII_VSC8244_IMASK,  in vsc82xx_config_intr()
319 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
329 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc8221_config_init()
352 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
354 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
356 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
358 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
361 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
363 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()