93 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);  in bcm7xxx_28nm_b0_afe_config_init()
144 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
172 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
296 	ret = phy_write(dev, location, v);  in phy_set_clr_bits()
314 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);  in bcm7xxx_28nm_ephy_01_afe_config_init()
319 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
329 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
385 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
389 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
395 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
399 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
404 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
408 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
414 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
418 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
431 	phy_write(phydev, MII_BMCR,  in bcm7xxx_28nm_ephy_eee_enable()
483 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);  in bcm7xxx_config_init()
493 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
497 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
499 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
529 		ret = phy_write(phydev,  in bcm7xxx_suspend()