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Searched refs:mvpp2_write (Results 1 – 4 of 4) sorted by relevance

/Linux-v4.19/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2_cls.c327 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_cls_flow_hits()
336 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, index); in mvpp2_cls_flow_read()
346 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); in mvpp2_cls_flow_write()
347 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); in mvpp2_cls_flow_write()
348 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); in mvpp2_cls_flow_write()
349 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); in mvpp2_cls_flow_write()
354 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_cls_lookup_hits()
365 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); in mvpp2_cls_lookup_read()
378 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); in mvpp2_cls_lookup_write()
379 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); in mvpp2_cls_lookup_write()
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Dmvpp2_main.c75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
355 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
357 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
361 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
380 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
485 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
524 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); in mvpp2_bm_init()
526 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); in mvpp2_bm_init()
574 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
595 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
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Dmvpp2_prs.c33 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
80 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_hw_inv()
81 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), in mvpp2_prs_hw_inv()
1076 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); in mvpp2_prs_hw_port_init()
1082 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
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Dmvpp2.h1095 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);