75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)  in mvpp2_write()  function
355 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),  in mvpp2_bm_pool_create()
357 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);  in mvpp2_bm_pool_create()
361 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);  in mvpp2_bm_pool_create()
380 	mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);  in mvpp2_bm_pool_bufsize_set()
485 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);  in mvpp2_bm_pool_destroy()
524 		mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);  in mvpp2_bm_init()
526 		mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);  in mvpp2_bm_init()
574 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_long_pool_set()
595 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_short_pool_set()
858 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_interrupts_enable()
869 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_interrupts_disable()
877 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_qvec_interrupt_enable()
885 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_qvec_interrupt_disable()
1424 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,  in mvpp2_defaults_set()
1426 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);  in mvpp2_defaults_set()
1431 		mvpp2_write(port->priv,  in mvpp2_defaults_set()
1438 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,  in mvpp2_defaults_set()
1444 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);  in mvpp2_defaults_set()
1446 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);  in mvpp2_defaults_set()
1449 	mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),  in mvpp2_defaults_set()
1459 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_defaults_set()
1476 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_enable()
1489 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_disable()
1511 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_egress_enable()
1512 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);  in mvpp2_egress_enable()
1525 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_egress_disable()
1529 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,  in mvpp2_egress_disable()
1574 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);  in mvpp2_rxq_status_update()
1604 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_offset_set()
1812 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_txp_max_tx_size_set()
1818 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);  in mvpp2_txp_max_tx_size_set()
1827 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);  in mvpp2_txp_max_tx_size_set()
1839 			mvpp2_write(port->priv,  in mvpp2_txp_max_tx_size_set()
1914 	mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);  in mvpp2_rx_time_coal_set()
1930 	mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);  in mvpp2_tx_time_coal_set()
2047 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);  in mvpp2_aggr_txq_init()
2048 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu),  in mvpp2_aggr_txq_init()
2074 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);  in mvpp2_rxq_init()
2148 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);  in mvpp2_rxq_deinit()
2205 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_txq_init()
2211 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);  in mvpp2_txq_init()
2214 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),  in mvpp2_txq_init()
2278 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);  in mvpp2_txq_deinit()
2348 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);  in mvpp2_cleanup_txqs()
2359 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);  in mvpp2_cleanup_txqs()
3053 		mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);  in mvpp2_poll()
4063 		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),  in mvpp2_rx_irqs_setup()
4077 		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);  in mvpp2_rx_irqs_setup()
4081 		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);  in mvpp2_rx_irqs_setup()
4872 		mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);  in mvpp2_conf_mbus_windows()
4873 		mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);  in mvpp2_conf_mbus_windows()
4876 			mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);  in mvpp2_conf_mbus_windows()
4884 		mvpp2_write(priv, MVPP2_WIN_BASE(i),  in mvpp2_conf_mbus_windows()
4888 		mvpp2_write(priv, MVPP2_WIN_SIZE(i),  in mvpp2_conf_mbus_windows()
4894 	mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);  in mvpp2_conf_mbus_windows()
4903 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),  in mvpp2_rx_fifo_init()
4905 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),  in mvpp2_rx_fifo_init()
4909 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,  in mvpp2_rx_fifo_init()
4911 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);  in mvpp2_rx_fifo_init()
4925 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),  in mvpp22_rx_fifo_init()
4927 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),  in mvpp22_rx_fifo_init()
4930 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),  in mvpp22_rx_fifo_init()
4932 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),  in mvpp22_rx_fifo_init()
4936 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),  in mvpp22_rx_fifo_init()
4938 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),  in mvpp22_rx_fifo_init()
4942 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,  in mvpp22_rx_fifo_init()
4944 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);  in mvpp22_rx_fifo_init()
4963 		mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);  in mvpp22_tx_fifo_init()
4964 		mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);  in mvpp22_tx_fifo_init()
4972 	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);  in mvpp2_axi_init()
4987 	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
4988 	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
4991 	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
4992 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
4993 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
4994 	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
4997 	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
4998 	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
5004 	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);  in mvpp2_axi_init()
5005 	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);  in mvpp2_axi_init()
5012 	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);  in mvpp2_axi_init()
5019 	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);  in mvpp2_axi_init()
5076 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);  in mvpp2_init()