327 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);  in mvpp2_cls_flow_hits()
336 	mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, index);  in mvpp2_cls_flow_read()
346 	mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);  in mvpp2_cls_flow_write()
347 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG,  fe->data[0]);  in mvpp2_cls_flow_write()
348 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG,  fe->data[1]);  in mvpp2_cls_flow_write()
349 	mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG,  fe->data[2]);  in mvpp2_cls_flow_write()
354 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);  in mvpp2_cls_lookup_hits()
365 	mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);  in mvpp2_cls_lookup_read()
378 	mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);  in mvpp2_cls_lookup_write()
379 	mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);  in mvpp2_cls_lookup_write()
743 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index);  in mvpp2_cls_c2_write()
746 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]);  in mvpp2_cls_c2_write()
747 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]);  in mvpp2_cls_c2_write()
748 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]);  in mvpp2_cls_c2_write()
749 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]);  in mvpp2_cls_c2_write()
750 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]);  in mvpp2_cls_c2_write()
752 	mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act);  in mvpp2_cls_c2_write()
754 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]);  in mvpp2_cls_c2_write()
755 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]);  in mvpp2_cls_c2_write()
756 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]);  in mvpp2_cls_c2_write()
757 	mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]);  in mvpp2_cls_c2_write()
763 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, index);  in mvpp2_cls_c2_read()
823 	mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);  in mvpp2_cls_init()
854 	mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);  in mvpp2_cls_port_config()
878 	mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2_index);  in mvpp2_cls_c2_hit_count()
920 	mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),  in mvpp2_cls_oversize_rxq_set()
923 	mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),  in mvpp2_cls_oversize_rxq_set()
928 	mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);  in mvpp2_cls_oversize_rxq_set()
958 		mvpp2_write(priv, MVPP22_RSS_INDEX, sel);  in mvpp22_rss_fill_table()
960 		mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY,  in mvpp22_rss_fill_table()
1048 	mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(port->id));  in mvpp22_rss_port_init()
1049 	mvpp2_write(priv, MVPP22_RSS_WIDTH, 8);  in mvpp22_rss_port_init()
1054 	mvpp2_write(priv, MVPP22_RSS_INDEX,  in mvpp22_rss_port_init()
1056 	mvpp2_write(priv, MVPP22_RXQ2RSS_TABLE,  in mvpp22_rss_port_init()