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/Linux-v4.19/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c37 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 *value = gpu->identity.model; in etnaviv_gpu_get_param()
45 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
49 *value = gpu->identity.features; in etnaviv_gpu_get_param()
53 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features5; in etnaviv_gpu_get_param()
[all …]
Detnaviv_buffer.c86 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
91 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
99 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
101 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
112 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
118 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
146 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
155 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
157 struct etnaviv_cmdbuf *buffer = &gpu->buffer; in etnaviv_buffer_init()
159 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_init()
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Detnaviv_drv.c28 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
35 priv->gpu[i] = NULL; in load_gpu()
51 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
54 if (gpu) { in etnaviv_open()
55 rq = &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; in etnaviv_open()
73 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
75 if (gpu) { in etnaviv_postclose()
76 mutex_lock(&gpu->lock); in etnaviv_postclose()
77 if (gpu->lastctx == ctx) in etnaviv_postclose()
78 gpu->lastctx = NULL; in etnaviv_postclose()
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Detnaviv_sched.c80 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
88 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
96 if (fence_completed(gpu, submit->out_fence->seqno)) in etnaviv_sched_timedout_job()
104 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
105 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
107 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
114 kthread_park(gpu->sched.thread); in etnaviv_sched_timedout_job()
115 drm_sched_hw_job_reset(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
118 etnaviv_core_dump(gpu); in etnaviv_sched_timedout_job()
119 etnaviv_gpu_recover_hang(gpu); in etnaviv_sched_timedout_job()
[all …]
Detnaviv_gpu.h86 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
154 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
156 writel(data, gpu->mmio + reg); in gpu_write()
159 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
161 return readl(gpu->mmio + reg); in gpu_read()
164 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) in fence_completed() argument
166 return fence_after_eq(gpu->completed_fence, fence); in fence_completed()
169 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
171 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
172 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
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Detnaviv_iommu.c125 void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu) in etnaviv_iommuv1_restore() argument
128 to_etnaviv_domain(gpu->mmu->domain); in etnaviv_iommuv1_restore()
132 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base); in etnaviv_iommuv1_restore()
133 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base); in etnaviv_iommuv1_restore()
134 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base); in etnaviv_iommuv1_restore()
135 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base); in etnaviv_iommuv1_restore()
136 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base); in etnaviv_iommuv1_restore()
141 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
142 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
143 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
[all …]
Detnaviv_iommu_v2.c228 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu) in etnaviv_iommuv2_restore_nonsec() argument
231 to_etnaviv_domain(gpu->mmu->domain); in etnaviv_iommuv2_restore_nonsec()
235 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
238 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
241 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
243 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
245 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
248 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu) in etnaviv_iommuv2_restore_sec() argument
251 to_etnaviv_domain(gpu->mmu->domain); in etnaviv_iommuv2_restore_sec()
255 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
[all …]
Detnaviv_dump.c80 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers() argument
87 reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); in etnaviv_core_dump_registers()
94 struct etnaviv_gpu *gpu, size_t mmu_size) in etnaviv_core_dump_mmu() argument
96 etnaviv_iommu_dump(gpu->mmu, iter->data); in etnaviv_core_dump_mmu()
111 void etnaviv_core_dump(struct etnaviv_gpu *gpu) in etnaviv_core_dump() argument
127 mmu_size = etnaviv_iommu_dump_size(gpu->mmu); in etnaviv_core_dump()
134 mmu_size + gpu->buffer.size; in etnaviv_core_dump()
137 spin_lock(&gpu->sched.job_list_lock); in etnaviv_core_dump()
138 list_for_each_entry(s_job, &gpu->sched.ring_mirror_list, node) { in etnaviv_core_dump()
143 spin_unlock(&gpu->sched.job_list_lock); in etnaviv_core_dump()
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/Linux-v4.19/drivers/gpu/drm/msm/
Dmsm_gpu.c36 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_target() local
44 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
53 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_dev_status() local
58 status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status()
59 gpu->funcs->gpu_busy(gpu, &cycles); in msm_devfreq_get_dev_status()
61 status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq; in msm_devfreq_get_dev_status()
63 gpu->devfreq.busy_cycles = cycles; in msm_devfreq_get_dev_status()
66 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status()
67 gpu->devfreq.time = time; in msm_devfreq_get_dev_status()
74 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); in msm_devfreq_get_cur_freq() local
[all …]
Dmsm_gpu.h55 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
56 int (*hw_init)(struct msm_gpu *gpu);
57 int (*pm_suspend)(struct msm_gpu *gpu);
58 int (*pm_resume)(struct msm_gpu *gpu);
59 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
63 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 void (*recover)(struct msm_gpu *gpu);
65 void (*destroy)(struct msm_gpu *gpu);
68 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
[all …]
Dmsm_debugfs.c35 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
42 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
43 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
55 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
62 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release()
74 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local
78 if (!gpu) in msm_gpu_open()
89 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_open()
90 show_priv->state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_open()
91 pm_runtime_put_sync(&gpu->pdev->dev); in msm_gpu_open()
[all …]
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c34 static void a4xx_dump(struct msm_gpu *gpu);
35 static bool a4xx_idle(struct msm_gpu *gpu);
41 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
43 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
46 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
48 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
50 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
52 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
54 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
56 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
[all …]
Da3xx_gpu.c43 static void a3xx_dump(struct msm_gpu *gpu);
44 static bool a3xx_idle(struct msm_gpu *gpu);
46 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
48 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
69 gpu->funcs->flush(gpu, ring); in a3xx_me_init()
70 return a3xx_idle(gpu); in a3xx_me_init()
73 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
75 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
80 DBG("%s", gpu->name); in a3xx_hw_init()
84 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
[all …]
Da6xx_gpu.c10 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
12 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
20 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
24 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
28 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
31 if (!adreno_idle(gpu, ring)) in a6xx_idle()
34 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
36 gpu->name, __builtin_return_address(0), in a6xx_idle()
37 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
38 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
[all …]
Da5xx_gpu.c30 static void a5xx_dump(struct msm_gpu *gpu);
34 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname) in zap_shader_load_mdt() argument
36 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
64 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
93 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { in zap_shader_load_mdt()
122 static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_flush() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
144 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
147 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit, in a5xx_submit_in_rb() argument
150 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
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Da5xx_power.c100 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
102 struct drm_device *dev = gpu->dev; in _get_mvolts()
119 static void a5xx_lm_setup(struct msm_gpu *gpu) in a5xx_lm_setup() argument
121 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_lm_setup()
127 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a5xx_lm_setup()
131 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a5xx_lm_setup()
132 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a5xx_lm_setup()
133 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a5xx_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a5xx_lm_setup()
138 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a5xx_lm_setup()
[all …]
Dadreno_gpu.h77 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
158 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) in adreno_is_a3xx() argument
160 return (gpu->revn >= 300) && (gpu->revn < 400); in adreno_is_a3xx()
163 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument
165 return gpu->revn == 305; in adreno_is_a305()
168 static inline bool adreno_is_a306(struct adreno_gpu *gpu) in adreno_is_a306() argument
171 return gpu->revn == 307; in adreno_is_a306()
174 static inline bool adreno_is_a320(struct adreno_gpu *gpu) in adreno_is_a320() argument
176 return gpu->revn == 320; in adreno_is_a320()
179 static inline bool adreno_is_a330(struct adreno_gpu *gpu) in adreno_is_a330() argument
[all …]
Da5xx_preempt.c34 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
43 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
49 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
61 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
65 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
70 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
72 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
88 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
89 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
95 dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer()
[all …]
Da5xx_debugfs.c21 static int pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
28 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
30 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 static int me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
43 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
45 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
51 static int meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
56 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
60 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
66 static int roq_print(struct msm_gpu *gpu, struct drm_printer *p) in roq_print() argument
[all …]
Dadreno_gpu.c28 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) in adreno_get_param() argument
30 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_get_param()
55 pm_runtime_get_sync(&gpu->pdev->dev); in adreno_get_param()
56 ret = adreno_gpu->funcs->get_timestamp(gpu, value); in adreno_get_param()
57 pm_runtime_put_autosuspend(&gpu->pdev->dev); in adreno_get_param()
63 *value = gpu->nr_rings; in adreno_get_param()
66 DBG("%s: invalid param: %u", gpu->name, param); in adreno_get_param()
176 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, in adreno_fw_create_bo() argument
182 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, in adreno_fw_create_bo()
183 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); in adreno_fw_create_bo()
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Dadreno_device.c169 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
174 gpu = platform_get_drvdata(pdev); in adreno_load_gpu()
176 if (!gpu) { in adreno_load_gpu()
181 adreno_gpu = to_adreno_gpu(gpu); in adreno_load_gpu()
203 ret = msm_gpu_hw_init(gpu); in adreno_load_gpu()
212 if (gpu->funcs->debugfs_init) { in adreno_load_gpu()
213 gpu->funcs->debugfs_init(gpu, dev->primary); in adreno_load_gpu()
214 gpu->funcs->debugfs_init(gpu, dev->render); in adreno_load_gpu()
218 return gpu; in adreno_load_gpu()
276 struct msm_gpu *gpu; in adreno_bind() local
[all …]
Da5xx_gpu.h53 int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
136 int a5xx_power_init(struct msm_gpu *gpu);
137 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
139 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
144 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
152 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
153 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
155 void a5xx_preempt_init(struct msm_gpu *gpu);
156 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
157 void a5xx_preempt_trigger(struct msm_gpu *gpu);
[all …]
/Linux-v4.19/Documentation/gpu/
Di915.rst19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
[all …]
Damdgpu.rst13 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
31 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
34 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
40 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
43 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
49 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
52 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
58 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
61 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
67 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
[all …]
Ddrm-kms-helpers.rst53 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
59 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
65 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
74 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
80 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
86 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
92 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
98 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
104 .. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c
107 .. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c
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