28 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)  in adreno_get_param()  argument
30 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_get_param()
55 			pm_runtime_get_sync(&gpu->pdev->dev);  in adreno_get_param()
56 			ret = adreno_gpu->funcs->get_timestamp(gpu, value);  in adreno_get_param()
57 			pm_runtime_put_autosuspend(&gpu->pdev->dev);  in adreno_get_param()
63 		*value = gpu->nr_rings;  in adreno_get_param()
66 		DBG("%s: invalid param: %u", gpu->name, param);  in adreno_get_param()
176 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,  in adreno_fw_create_bo()  argument
182 	ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,  in adreno_fw_create_bo()
183 		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);  in adreno_fw_create_bo()
195 int adreno_hw_init(struct msm_gpu *gpu)  in adreno_hw_init()  argument
197 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_hw_init()
200 	DBG("%s", gpu->name);  in adreno_hw_init()
206 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_hw_init()
207 		struct msm_ringbuffer *ring = gpu->rb[i];  in adreno_hw_init()
212 		ret = msm_gem_get_iova(ring->bo, gpu->aspace, &ring->iova);  in adreno_hw_init()
215 			dev_err(gpu->dev->dev,  in adreno_hw_init()
240 		REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);  in adreno_hw_init()
245 			rbmemptr(gpu->rb[0], rptr));  in adreno_hw_init()
262 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)  in adreno_active_ring()  argument
264 	return gpu->rb[0];  in adreno_active_ring()
267 void adreno_recover(struct msm_gpu *gpu)  in adreno_recover()  argument
269 	struct drm_device *dev = gpu->dev;  in adreno_recover()
275 	gpu->funcs->pm_suspend(gpu);  in adreno_recover()
276 	gpu->funcs->pm_resume(gpu);  in adreno_recover()
278 	ret = msm_gpu_hw_init(gpu);  in adreno_recover()
285 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,  in adreno_submit()  argument
288 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_submit()
289 	struct msm_drm_private *priv = gpu->dev->dev_private;  in adreno_submit()
342 	gpu->funcs->flush(gpu, ring);  in adreno_submit()
345 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in adreno_flush()  argument
347 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_flush()
366 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in adreno_idle()  argument
368 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_idle()
377 		gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);  in adreno_idle()
382 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)  in adreno_gpu_state_get()  argument
384 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_gpu_state_get()
391 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_gpu_state_get()
394 		state->ring[i].fence = gpu->rb[i]->memptrs->fence;  in adreno_gpu_state_get()
395 		state->ring[i].iova = gpu->rb[i]->iova;  in adreno_gpu_state_get()
396 		state->ring[i].seqno = gpu->rb[i]->seqno;  in adreno_gpu_state_get()
397 		state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);  in adreno_gpu_state_get()
398 		state->ring[i].wptr = get_wptr(gpu->rb[i]);  in adreno_gpu_state_get()
405 			if (gpu->rb[i]->start[j])  in adreno_gpu_state_get()
411 				memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);  in adreno_gpu_state_get()
433 				state->registers[pos++] = gpu_read(gpu, addr);  in adreno_gpu_state_get()
510 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,  in adreno_show()  argument
513 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_show()
528 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_show()
570 void adreno_dump_info(struct msm_gpu *gpu)  in adreno_dump_info()  argument
572 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_dump_info()
580 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_dump_info()
581 		struct msm_ringbuffer *ring = gpu->rb[i];  in adreno_dump_info()
593 void adreno_dump(struct msm_gpu *gpu)  in adreno_dump()  argument
595 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_dump()
599 	printk("IO:region %s 00000000 00020000\n", gpu->name);  in adreno_dump()
606 			uint32_t val = gpu_read(gpu, addr);  in adreno_dump()
614 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);  in ring_freewords()
625 		DRM_DEV_ERROR(ring->gpu->dev->dev,  in adreno_wait_ring()
662 		struct msm_gpu *gpu)  in adreno_get_pwrlevels()  argument
668 	gpu->fast_rate = 0;  in adreno_get_pwrlevels()
683 			gpu->fast_rate = freq;  in adreno_get_pwrlevels()
688 	if (!gpu->fast_rate) {  in adreno_get_pwrlevels()
692 		gpu->fast_rate = 200000000;  in adreno_get_pwrlevels()
695 	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);  in adreno_get_pwrlevels()
706 	struct msm_gpu *gpu = &adreno_gpu->base;  in adreno_gpu_init()  local
722 	adreno_get_pwrlevels(&pdev->dev, gpu);  in adreno_gpu_init()