| /Linux-v4.19/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_ctl.c | 46 u32 flush_mask; member
479 u32 flush_mask) in fix_sw_flush() argument
484 (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) in fix_sw_flush()
493 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, in fix_for_single_flush() argument
499 DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); in fix_for_single_flush()
501 ctl_mgr->single_flush_pending_mask |= (*flush_mask); in fix_for_single_flush()
502 *flush_mask = 0; in fix_for_single_flush()
506 *flush_mask = ctl_mgr->single_flush_pending_mask; in fix_for_single_flush()
512 DBG("Single FLUSH mask %x,ID %d", *flush_mask, in fix_for_single_flush()
536 u32 flush_mask, bool start) in mdp5_ctl_commit() argument
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| D | mdp5_crtc.c | 95 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) in crtc_flush() argument
104 DBG("%s: flush=%08x", crtc->name, flush_mask); in crtc_flush()
106 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
119 uint32_t flush_mask = 0; in crtc_flush_all() local
128 flush_mask |= mdp5_plane_get_flush(plane); in crtc_flush_all()
132 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); in crtc_flush_all()
136 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); in crtc_flush_all()
138 return crtc_flush(crtc, flush_mask); in crtc_flush_all()
871 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_set() local
932 crtc_flush(crtc, flush_mask); in mdp5_crtc_cursor_set()
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| D | mdp5_mixer.h | 31 uint32_t flush_mask; /* used to commit LM registers */ member
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| D | mdp5_pipe.h | 34 uint32_t flush_mask; /* used to commit pipe registers */ member
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| D | mdp5_ctl.h | 81 u32 flush_mask, bool start);
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| D | mdp5_mixer.c | 169 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); in mdp5_mixer_init()
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| D | mdp5_pipe.c | 175 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); in mdp5_pipe_init()
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| D | mdp5_plane.c | 1067 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush()
1070 mask |= pstate->r_hwpipe->flush_mask; in mdp5_plane_get_flush()
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| /Linux-v4.19/arch/x86/platform/uv/ |
| D | tlb_uv.c | 899 static int uv_flush_send_and_wait(struct cpumask *flush_mask, in uv_flush_send_and_wait() argument
1051 static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, in set_distrib_bits() argument
1059 for_each_cpu(cpu, flush_mask) { in set_distrib_bits()
1111 struct cpumask *flush_mask; in uv_flush_tlb_others() local
1147 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); in uv_flush_tlb_others()
1149 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); in uv_flush_tlb_others()
1157 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) in uv_flush_tlb_others()
1185 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc)) in uv_flush_tlb_others()
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| /Linux-v4.19/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 486 u32 flush_mask = 0; in dpu_encoder_phys_vid_enable() local
522 ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx); in dpu_encoder_phys_vid_enable()
523 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_vid_enable()
527 ctl->idx - CTL_0, flush_mask); in dpu_encoder_phys_vid_enable()
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| D | dpu_crtc.c | 349 u32 flush_mask; in _dpu_crtc_blend_setup_mixer() local
372 dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); in _dpu_crtc_blend_setup_mixer()
406 mixer[lm_idx].flush_mask |= flush_mask; in _dpu_crtc_blend_setup_mixer()
453 mixer[i].flush_mask = 0; in _dpu_crtc_blend_setup()
470 mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, in _dpu_crtc_blend_setup()
474 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_blend_setup()
480 mixer[i].flush_mask); in _dpu_crtc_blend_setup()
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| D | dpu_crtc.h | 96 u32 flush_mask; member
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| D | dpu_encoder_phys_cmd.c | 506 u32 flush_mask = 0; in dpu_encoder_phys_cmd_enable_helper() local
521 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); in dpu_encoder_phys_cmd_enable_helper()
522 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_cmd_enable_helper()
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