1 /*
2  *	SGI UltraViolet TLB flush routines.
3  *
4  *	(c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
5  *
6  *	This code is released under the GNU General Public License version 2 or
7  *	later.
8  */
9 #include <linux/seq_file.h>
10 #include <linux/proc_fs.h>
11 #include <linux/debugfs.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 
16 #include <asm/mmu_context.h>
17 #include <asm/uv/uv.h>
18 #include <asm/uv/uv_mmrs.h>
19 #include <asm/uv/uv_hub.h>
20 #include <asm/uv/uv_bau.h>
21 #include <asm/apic.h>
22 #include <asm/tsc.h>
23 #include <asm/irq_vectors.h>
24 #include <asm/timer.h>
25 
26 static struct bau_operations ops __ro_after_init;
27 
28 /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
29 static const int timeout_base_ns[] = {
30 		20,
31 		160,
32 		1280,
33 		10240,
34 		81920,
35 		655360,
36 		5242880,
37 		167772160
38 };
39 
40 static int timeout_us;
41 static bool nobau = true;
42 static int nobau_perm;
43 
44 /* tunables: */
45 static int max_concurr		= MAX_BAU_CONCURRENT;
46 static int max_concurr_const	= MAX_BAU_CONCURRENT;
47 static int plugged_delay	= PLUGGED_DELAY;
48 static int plugsb4reset		= PLUGSB4RESET;
49 static int giveup_limit		= GIVEUP_LIMIT;
50 static int timeoutsb4reset	= TIMEOUTSB4RESET;
51 static int ipi_reset_limit	= IPI_RESET_LIMIT;
52 static int complete_threshold	= COMPLETE_THRESHOLD;
53 static int congested_respns_us	= CONGESTED_RESPONSE_US;
54 static int congested_reps	= CONGESTED_REPS;
55 static int disabled_period	= DISABLED_PERIOD;
56 
57 static struct tunables tunables[] = {
58 	{&max_concurr,           MAX_BAU_CONCURRENT}, /* must be [0] */
59 	{&plugged_delay,         PLUGGED_DELAY},
60 	{&plugsb4reset,          PLUGSB4RESET},
61 	{&timeoutsb4reset,       TIMEOUTSB4RESET},
62 	{&ipi_reset_limit,       IPI_RESET_LIMIT},
63 	{&complete_threshold,    COMPLETE_THRESHOLD},
64 	{&congested_respns_us,   CONGESTED_RESPONSE_US},
65 	{&congested_reps,        CONGESTED_REPS},
66 	{&disabled_period,       DISABLED_PERIOD},
67 	{&giveup_limit,          GIVEUP_LIMIT}
68 };
69 
70 static struct dentry *tunables_dir;
71 static struct dentry *tunables_file;
72 
73 /* these correspond to the statistics printed by ptc_seq_show() */
74 static char *stat_description[] = {
75 	"sent:     number of shootdown messages sent",
76 	"stime:    time spent sending messages",
77 	"numuvhubs: number of hubs targeted with shootdown",
78 	"numuvhubs16: number times 16 or more hubs targeted",
79 	"numuvhubs8: number times 8 or more hubs targeted",
80 	"numuvhubs4: number times 4 or more hubs targeted",
81 	"numuvhubs2: number times 2 or more hubs targeted",
82 	"numuvhubs1: number times 1 hub targeted",
83 	"numcpus:  number of cpus targeted with shootdown",
84 	"dto:      number of destination timeouts",
85 	"retries:  destination timeout retries sent",
86 	"rok:   :  destination timeouts successfully retried",
87 	"resetp:   ipi-style resource resets for plugs",
88 	"resett:   ipi-style resource resets for timeouts",
89 	"giveup:   fall-backs to ipi-style shootdowns",
90 	"sto:      number of source timeouts",
91 	"bz:       number of stay-busy's",
92 	"throt:    number times spun in throttle",
93 	"swack:   image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
94 	"recv:     shootdown messages received",
95 	"rtime:    time spent processing messages",
96 	"all:      shootdown all-tlb messages",
97 	"one:      shootdown one-tlb messages",
98 	"mult:     interrupts that found multiple messages",
99 	"none:     interrupts that found no messages",
100 	"retry:    number of retry messages processed",
101 	"canc:     number messages canceled by retries",
102 	"nocan:    number retries that found nothing to cancel",
103 	"reset:    number of ipi-style reset requests processed",
104 	"rcan:     number messages canceled by reset requests",
105 	"disable:  number times use of the BAU was disabled",
106 	"enable:   number times use of the BAU was re-enabled"
107 };
108 
setup_bau(char * arg)109 static int __init setup_bau(char *arg)
110 {
111 	int result;
112 
113 	if (!arg)
114 		return -EINVAL;
115 
116 	result = strtobool(arg, &nobau);
117 	if (result)
118 		return result;
119 
120 	/* we need to flip the logic here, so that bau=y sets nobau to false */
121 	nobau = !nobau;
122 
123 	if (!nobau)
124 		pr_info("UV BAU Enabled\n");
125 	else
126 		pr_info("UV BAU Disabled\n");
127 
128 	return 0;
129 }
130 early_param("bau", setup_bau);
131 
132 /* base pnode in this partition */
133 static int uv_base_pnode __read_mostly;
134 
135 static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
136 static DEFINE_PER_CPU(struct bau_control, bau_control);
137 static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
138 
139 static void
set_bau_on(void)140 set_bau_on(void)
141 {
142 	int cpu;
143 	struct bau_control *bcp;
144 
145 	if (nobau_perm) {
146 		pr_info("BAU not initialized; cannot be turned on\n");
147 		return;
148 	}
149 	nobau = false;
150 	for_each_present_cpu(cpu) {
151 		bcp = &per_cpu(bau_control, cpu);
152 		bcp->nobau = false;
153 	}
154 	pr_info("BAU turned on\n");
155 	return;
156 }
157 
158 static void
set_bau_off(void)159 set_bau_off(void)
160 {
161 	int cpu;
162 	struct bau_control *bcp;
163 
164 	nobau = true;
165 	for_each_present_cpu(cpu) {
166 		bcp = &per_cpu(bau_control, cpu);
167 		bcp->nobau = true;
168 	}
169 	pr_info("BAU turned off\n");
170 	return;
171 }
172 
173 /*
174  * Determine the first node on a uvhub. 'Nodes' are used for kernel
175  * memory allocation.
176  */
uvhub_to_first_node(int uvhub)177 static int __init uvhub_to_first_node(int uvhub)
178 {
179 	int node, b;
180 
181 	for_each_online_node(node) {
182 		b = uv_node_to_blade_id(node);
183 		if (uvhub == b)
184 			return node;
185 	}
186 	return -1;
187 }
188 
189 /*
190  * Determine the apicid of the first cpu on a uvhub.
191  */
uvhub_to_first_apicid(int uvhub)192 static int __init uvhub_to_first_apicid(int uvhub)
193 {
194 	int cpu;
195 
196 	for_each_present_cpu(cpu)
197 		if (uvhub == uv_cpu_to_blade_id(cpu))
198 			return per_cpu(x86_cpu_to_apicid, cpu);
199 	return -1;
200 }
201 
202 /*
203  * Free a software acknowledge hardware resource by clearing its Pending
204  * bit. This will return a reply to the sender.
205  * If the message has timed out, a reply has already been sent by the
206  * hardware but the resource has not been released. In that case our
207  * clear of the Timeout bit (as well) will free the resource. No reply will
208  * be sent (the hardware will only do one reply per message).
209  */
reply_to_message(struct msg_desc * mdp,struct bau_control * bcp,int do_acknowledge)210 static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
211 						int do_acknowledge)
212 {
213 	unsigned long dw;
214 	struct bau_pq_entry *msg;
215 
216 	msg = mdp->msg;
217 	if (!msg->canceled && do_acknowledge) {
218 		dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
219 		ops.write_l_sw_ack(dw);
220 	}
221 	msg->replied_to = 1;
222 	msg->swack_vec = 0;
223 }
224 
225 /*
226  * Process the receipt of a RETRY message
227  */
bau_process_retry_msg(struct msg_desc * mdp,struct bau_control * bcp)228 static void bau_process_retry_msg(struct msg_desc *mdp,
229 					struct bau_control *bcp)
230 {
231 	int i;
232 	int cancel_count = 0;
233 	unsigned long msg_res;
234 	unsigned long mmr = 0;
235 	struct bau_pq_entry *msg = mdp->msg;
236 	struct bau_pq_entry *msg2;
237 	struct ptc_stats *stat = bcp->statp;
238 
239 	stat->d_retries++;
240 	/*
241 	 * cancel any message from msg+1 to the retry itself
242 	 */
243 	for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
244 		if (msg2 > mdp->queue_last)
245 			msg2 = mdp->queue_first;
246 		if (msg2 == msg)
247 			break;
248 
249 		/* same conditions for cancellation as do_reset */
250 		if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
251 		    (msg2->swack_vec) && ((msg2->swack_vec &
252 			msg->swack_vec) == 0) &&
253 		    (msg2->sending_cpu == msg->sending_cpu) &&
254 		    (msg2->msg_type != MSG_NOOP)) {
255 			mmr = ops.read_l_sw_ack();
256 			msg_res = msg2->swack_vec;
257 			/*
258 			 * This is a message retry; clear the resources held
259 			 * by the previous message only if they timed out.
260 			 * If it has not timed out we have an unexpected
261 			 * situation to report.
262 			 */
263 			if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
264 				unsigned long mr;
265 				/*
266 				 * Is the resource timed out?
267 				 * Make everyone ignore the cancelled message.
268 				 */
269 				msg2->canceled = 1;
270 				stat->d_canceled++;
271 				cancel_count++;
272 				mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
273 				ops.write_l_sw_ack(mr);
274 			}
275 		}
276 	}
277 	if (!cancel_count)
278 		stat->d_nocanceled++;
279 }
280 
281 /*
282  * Do all the things a cpu should do for a TLB shootdown message.
283  * Other cpu's may come here at the same time for this message.
284  */
bau_process_message(struct msg_desc * mdp,struct bau_control * bcp,int do_acknowledge)285 static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
286 						int do_acknowledge)
287 {
288 	short socket_ack_count = 0;
289 	short *sp;
290 	struct atomic_short *asp;
291 	struct ptc_stats *stat = bcp->statp;
292 	struct bau_pq_entry *msg = mdp->msg;
293 	struct bau_control *smaster = bcp->socket_master;
294 
295 	/*
296 	 * This must be a normal message, or retry of a normal message
297 	 */
298 	if (msg->address == TLB_FLUSH_ALL) {
299 		local_flush_tlb();
300 		stat->d_alltlb++;
301 	} else {
302 		__flush_tlb_one_user(msg->address);
303 		stat->d_onetlb++;
304 	}
305 	stat->d_requestee++;
306 
307 	/*
308 	 * One cpu on each uvhub has the additional job on a RETRY
309 	 * of releasing the resource held by the message that is
310 	 * being retried.  That message is identified by sending
311 	 * cpu number.
312 	 */
313 	if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
314 		bau_process_retry_msg(mdp, bcp);
315 
316 	/*
317 	 * This is a swack message, so we have to reply to it.
318 	 * Count each responding cpu on the socket. This avoids
319 	 * pinging the count's cache line back and forth between
320 	 * the sockets.
321 	 */
322 	sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
323 	asp = (struct atomic_short *)sp;
324 	socket_ack_count = atom_asr(1, asp);
325 	if (socket_ack_count == bcp->cpus_in_socket) {
326 		int msg_ack_count;
327 		/*
328 		 * Both sockets dump their completed count total into
329 		 * the message's count.
330 		 */
331 		*sp = 0;
332 		asp = (struct atomic_short *)&msg->acknowledge_count;
333 		msg_ack_count = atom_asr(socket_ack_count, asp);
334 
335 		if (msg_ack_count == bcp->cpus_in_uvhub) {
336 			/*
337 			 * All cpus in uvhub saw it; reply
338 			 * (unless we are in the UV2 workaround)
339 			 */
340 			reply_to_message(mdp, bcp, do_acknowledge);
341 		}
342 	}
343 
344 	return;
345 }
346 
347 /*
348  * Determine the first cpu on a pnode.
349  */
pnode_to_first_cpu(int pnode,struct bau_control * smaster)350 static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
351 {
352 	int cpu;
353 	struct hub_and_pnode *hpp;
354 
355 	for_each_present_cpu(cpu) {
356 		hpp = &smaster->thp[cpu];
357 		if (pnode == hpp->pnode)
358 			return cpu;
359 	}
360 	return -1;
361 }
362 
363 /*
364  * Last resort when we get a large number of destination timeouts is
365  * to clear resources held by a given cpu.
366  * Do this with IPI so that all messages in the BAU message queue
367  * can be identified by their nonzero swack_vec field.
368  *
369  * This is entered for a single cpu on the uvhub.
370  * The sender want's this uvhub to free a specific message's
371  * swack resources.
372  */
do_reset(void * ptr)373 static void do_reset(void *ptr)
374 {
375 	int i;
376 	struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
377 	struct reset_args *rap = (struct reset_args *)ptr;
378 	struct bau_pq_entry *msg;
379 	struct ptc_stats *stat = bcp->statp;
380 
381 	stat->d_resets++;
382 	/*
383 	 * We're looking for the given sender, and
384 	 * will free its swack resource.
385 	 * If all cpu's finally responded after the timeout, its
386 	 * message 'replied_to' was set.
387 	 */
388 	for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
389 		unsigned long msg_res;
390 		/* do_reset: same conditions for cancellation as
391 		   bau_process_retry_msg() */
392 		if ((msg->replied_to == 0) &&
393 		    (msg->canceled == 0) &&
394 		    (msg->sending_cpu == rap->sender) &&
395 		    (msg->swack_vec) &&
396 		    (msg->msg_type != MSG_NOOP)) {
397 			unsigned long mmr;
398 			unsigned long mr;
399 			/*
400 			 * make everyone else ignore this message
401 			 */
402 			msg->canceled = 1;
403 			/*
404 			 * only reset the resource if it is still pending
405 			 */
406 			mmr = ops.read_l_sw_ack();
407 			msg_res = msg->swack_vec;
408 			mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
409 			if (mmr & msg_res) {
410 				stat->d_rcanceled++;
411 				ops.write_l_sw_ack(mr);
412 			}
413 		}
414 	}
415 	return;
416 }
417 
418 /*
419  * Use IPI to get all target uvhubs to release resources held by
420  * a given sending cpu number.
421  */
reset_with_ipi(struct pnmask * distribution,struct bau_control * bcp)422 static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
423 {
424 	int pnode;
425 	int apnode;
426 	int maskbits;
427 	int sender = bcp->cpu;
428 	cpumask_t *mask = bcp->uvhub_master->cpumask;
429 	struct bau_control *smaster = bcp->socket_master;
430 	struct reset_args reset_args;
431 
432 	reset_args.sender = sender;
433 	cpumask_clear(mask);
434 	/* find a single cpu for each uvhub in this distribution mask */
435 	maskbits = sizeof(struct pnmask) * BITSPERBYTE;
436 	/* each bit is a pnode relative to the partition base pnode */
437 	for (pnode = 0; pnode < maskbits; pnode++) {
438 		int cpu;
439 		if (!bau_uvhub_isset(pnode, distribution))
440 			continue;
441 		apnode = pnode + bcp->partition_base_pnode;
442 		cpu = pnode_to_first_cpu(apnode, smaster);
443 		cpumask_set_cpu(cpu, mask);
444 	}
445 
446 	/* IPI all cpus; preemption is already disabled */
447 	smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
448 	return;
449 }
450 
451 /*
452  * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
453  * number, not an absolute. It converts a duration in cycles to a duration in
454  * ns.
455  */
cycles_2_ns(unsigned long long cyc)456 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
457 {
458 	struct cyc2ns_data data;
459 	unsigned long long ns;
460 
461 	cyc2ns_read_begin(&data);
462 	ns = mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
463 	cyc2ns_read_end();
464 
465 	return ns;
466 }
467 
468 /*
469  * The reverse of the above; converts a duration in ns to a duration in cycles.
470  */
ns_2_cycles(unsigned long long ns)471 static inline unsigned long long ns_2_cycles(unsigned long long ns)
472 {
473 	struct cyc2ns_data data;
474 	unsigned long long cyc;
475 
476 	cyc2ns_read_begin(&data);
477 	cyc = (ns << data.cyc2ns_shift) / data.cyc2ns_mul;
478 	cyc2ns_read_end();
479 
480 	return cyc;
481 }
482 
cycles_2_us(unsigned long long cyc)483 static inline unsigned long cycles_2_us(unsigned long long cyc)
484 {
485 	return cycles_2_ns(cyc) / NSEC_PER_USEC;
486 }
487 
sec_2_cycles(unsigned long sec)488 static inline cycles_t sec_2_cycles(unsigned long sec)
489 {
490 	return ns_2_cycles(sec * NSEC_PER_SEC);
491 }
492 
usec_2_cycles(unsigned long usec)493 static inline unsigned long long usec_2_cycles(unsigned long usec)
494 {
495 	return ns_2_cycles(usec * NSEC_PER_USEC);
496 }
497 
498 /*
499  * wait for all cpus on this hub to finish their sends and go quiet
500  * leaves uvhub_quiesce set so that no new broadcasts are started by
501  * bau_flush_send_and_wait()
502  */
quiesce_local_uvhub(struct bau_control * hmaster)503 static inline void quiesce_local_uvhub(struct bau_control *hmaster)
504 {
505 	atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
506 }
507 
508 /*
509  * mark this quiet-requestor as done
510  */
end_uvhub_quiesce(struct bau_control * hmaster)511 static inline void end_uvhub_quiesce(struct bau_control *hmaster)
512 {
513 	atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
514 }
515 
uv1_read_status(unsigned long mmr_offset,int right_shift)516 static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
517 {
518 	unsigned long descriptor_status;
519 
520 	descriptor_status = uv_read_local_mmr(mmr_offset);
521 	descriptor_status >>= right_shift;
522 	descriptor_status &= UV_ACT_STATUS_MASK;
523 	return descriptor_status;
524 }
525 
526 /*
527  * Wait for completion of a broadcast software ack message
528  * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
529  */
uv1_wait_completion(struct bau_desc * bau_desc,struct bau_control * bcp,long try)530 static int uv1_wait_completion(struct bau_desc *bau_desc,
531 				struct bau_control *bcp, long try)
532 {
533 	unsigned long descriptor_status;
534 	cycles_t ttm;
535 	u64 mmr_offset = bcp->status_mmr;
536 	int right_shift = bcp->status_index;
537 	struct ptc_stats *stat = bcp->statp;
538 
539 	descriptor_status = uv1_read_status(mmr_offset, right_shift);
540 	/* spin on the status MMR, waiting for it to go idle */
541 	while ((descriptor_status != DS_IDLE)) {
542 		/*
543 		 * Our software ack messages may be blocked because
544 		 * there are no swack resources available.  As long
545 		 * as none of them has timed out hardware will NACK
546 		 * our message and its state will stay IDLE.
547 		 */
548 		if (descriptor_status == DS_SOURCE_TIMEOUT) {
549 			stat->s_stimeout++;
550 			return FLUSH_GIVEUP;
551 		} else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
552 			stat->s_dtimeout++;
553 			ttm = get_cycles();
554 
555 			/*
556 			 * Our retries may be blocked by all destination
557 			 * swack resources being consumed, and a timeout
558 			 * pending.  In that case hardware returns the
559 			 * ERROR that looks like a destination timeout.
560 			 */
561 			if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
562 				bcp->conseccompletes = 0;
563 				return FLUSH_RETRY_PLUGGED;
564 			}
565 
566 			bcp->conseccompletes = 0;
567 			return FLUSH_RETRY_TIMEOUT;
568 		} else {
569 			/*
570 			 * descriptor_status is still BUSY
571 			 */
572 			cpu_relax();
573 		}
574 		descriptor_status = uv1_read_status(mmr_offset, right_shift);
575 	}
576 	bcp->conseccompletes++;
577 	return FLUSH_COMPLETE;
578 }
579 
580 /*
581  * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
582  * But not currently used.
583  */
uv2_3_read_status(unsigned long offset,int rshft,int desc)584 static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
585 {
586 	return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
587 }
588 
589 /*
590  * Entered when a bau descriptor has gone into a permanent busy wait because
591  * of a hardware bug.
592  * Workaround the bug.
593  */
handle_uv2_busy(struct bau_control * bcp)594 static int handle_uv2_busy(struct bau_control *bcp)
595 {
596 	struct ptc_stats *stat = bcp->statp;
597 
598 	stat->s_uv2_wars++;
599 	bcp->busy = 1;
600 	return FLUSH_GIVEUP;
601 }
602 
uv2_3_wait_completion(struct bau_desc * bau_desc,struct bau_control * bcp,long try)603 static int uv2_3_wait_completion(struct bau_desc *bau_desc,
604 				struct bau_control *bcp, long try)
605 {
606 	unsigned long descriptor_stat;
607 	cycles_t ttm;
608 	u64 mmr_offset = bcp->status_mmr;
609 	int right_shift = bcp->status_index;
610 	int desc = bcp->uvhub_cpu;
611 	long busy_reps = 0;
612 	struct ptc_stats *stat = bcp->statp;
613 
614 	descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
615 
616 	/* spin on the status MMR, waiting for it to go idle */
617 	while (descriptor_stat != UV2H_DESC_IDLE) {
618 		if (descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) {
619 			/*
620 			 * A h/w bug on the destination side may
621 			 * have prevented the message being marked
622 			 * pending, thus it doesn't get replied to
623 			 * and gets continually nacked until it times
624 			 * out with a SOURCE_TIMEOUT.
625 			 */
626 			stat->s_stimeout++;
627 			return FLUSH_GIVEUP;
628 		} else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
629 			ttm = get_cycles();
630 
631 			/*
632 			 * Our retries may be blocked by all destination
633 			 * swack resources being consumed, and a timeout
634 			 * pending.  In that case hardware returns the
635 			 * ERROR that looks like a destination timeout.
636 			 * Without using the extended status we have to
637 			 * deduce from the short time that this was a
638 			 * strong nack.
639 			 */
640 			if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
641 				bcp->conseccompletes = 0;
642 				stat->s_plugged++;
643 				/* FLUSH_RETRY_PLUGGED causes hang on boot */
644 				return FLUSH_GIVEUP;
645 			}
646 			stat->s_dtimeout++;
647 			bcp->conseccompletes = 0;
648 			/* FLUSH_RETRY_TIMEOUT causes hang on boot */
649 			return FLUSH_GIVEUP;
650 		} else {
651 			busy_reps++;
652 			if (busy_reps > 1000000) {
653 				/* not to hammer on the clock */
654 				busy_reps = 0;
655 				ttm = get_cycles();
656 				if ((ttm - bcp->send_message) > bcp->timeout_interval)
657 					return handle_uv2_busy(bcp);
658 			}
659 			/*
660 			 * descriptor_stat is still BUSY
661 			 */
662 			cpu_relax();
663 		}
664 		descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
665 	}
666 	bcp->conseccompletes++;
667 	return FLUSH_COMPLETE;
668 }
669 
670 /*
671  * Returns the status of current BAU message for cpu desc as a bit field
672  * [Error][Busy][Aux]
673  */
read_status(u64 status_mmr,int index,int desc)674 static u64 read_status(u64 status_mmr, int index, int desc)
675 {
676 	u64 stat;
677 
678 	stat = ((read_lmmr(status_mmr) >> index) & UV_ACT_STATUS_MASK) << 1;
679 	stat |= (read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_2) >> desc) & 0x1;
680 
681 	return stat;
682 }
683 
uv4_wait_completion(struct bau_desc * bau_desc,struct bau_control * bcp,long try)684 static int uv4_wait_completion(struct bau_desc *bau_desc,
685 				struct bau_control *bcp, long try)
686 {
687 	struct ptc_stats *stat = bcp->statp;
688 	u64 descriptor_stat;
689 	u64 mmr = bcp->status_mmr;
690 	int index = bcp->status_index;
691 	int desc = bcp->uvhub_cpu;
692 
693 	descriptor_stat = read_status(mmr, index, desc);
694 
695 	/* spin on the status MMR, waiting for it to go idle */
696 	while (descriptor_stat != UV2H_DESC_IDLE) {
697 		switch (descriptor_stat) {
698 		case UV2H_DESC_SOURCE_TIMEOUT:
699 			stat->s_stimeout++;
700 			return FLUSH_GIVEUP;
701 
702 		case UV2H_DESC_DEST_TIMEOUT:
703 			stat->s_dtimeout++;
704 			bcp->conseccompletes = 0;
705 			return FLUSH_RETRY_TIMEOUT;
706 
707 		case UV2H_DESC_DEST_STRONG_NACK:
708 			stat->s_plugged++;
709 			bcp->conseccompletes = 0;
710 			return FLUSH_RETRY_PLUGGED;
711 
712 		case UV2H_DESC_DEST_PUT_ERR:
713 			bcp->conseccompletes = 0;
714 			return FLUSH_GIVEUP;
715 
716 		default:
717 			/* descriptor_stat is still BUSY */
718 			cpu_relax();
719 		}
720 		descriptor_stat = read_status(mmr, index, desc);
721 	}
722 	bcp->conseccompletes++;
723 	return FLUSH_COMPLETE;
724 }
725 
726 /*
727  * Our retries are blocked by all destination sw ack resources being
728  * in use, and a timeout is pending. In that case hardware immediately
729  * returns the ERROR that looks like a destination timeout.
730  */
destination_plugged(struct bau_desc * bau_desc,struct bau_control * bcp,struct bau_control * hmaster,struct ptc_stats * stat)731 static void destination_plugged(struct bau_desc *bau_desc,
732 			struct bau_control *bcp,
733 			struct bau_control *hmaster, struct ptc_stats *stat)
734 {
735 	udelay(bcp->plugged_delay);
736 	bcp->plugged_tries++;
737 
738 	if (bcp->plugged_tries >= bcp->plugsb4reset) {
739 		bcp->plugged_tries = 0;
740 
741 		quiesce_local_uvhub(hmaster);
742 
743 		spin_lock(&hmaster->queue_lock);
744 		reset_with_ipi(&bau_desc->distribution, bcp);
745 		spin_unlock(&hmaster->queue_lock);
746 
747 		end_uvhub_quiesce(hmaster);
748 
749 		bcp->ipi_attempts++;
750 		stat->s_resets_plug++;
751 	}
752 }
753 
destination_timeout(struct bau_desc * bau_desc,struct bau_control * bcp,struct bau_control * hmaster,struct ptc_stats * stat)754 static void destination_timeout(struct bau_desc *bau_desc,
755 			struct bau_control *bcp, struct bau_control *hmaster,
756 			struct ptc_stats *stat)
757 {
758 	hmaster->max_concurr = 1;
759 	bcp->timeout_tries++;
760 	if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
761 		bcp->timeout_tries = 0;
762 
763 		quiesce_local_uvhub(hmaster);
764 
765 		spin_lock(&hmaster->queue_lock);
766 		reset_with_ipi(&bau_desc->distribution, bcp);
767 		spin_unlock(&hmaster->queue_lock);
768 
769 		end_uvhub_quiesce(hmaster);
770 
771 		bcp->ipi_attempts++;
772 		stat->s_resets_timeout++;
773 	}
774 }
775 
776 /*
777  * Stop all cpus on a uvhub from using the BAU for a period of time.
778  * This is reversed by check_enable.
779  */
disable_for_period(struct bau_control * bcp,struct ptc_stats * stat)780 static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
781 {
782 	int tcpu;
783 	struct bau_control *tbcp;
784 	struct bau_control *hmaster;
785 	cycles_t tm1;
786 
787 	hmaster = bcp->uvhub_master;
788 	spin_lock(&hmaster->disable_lock);
789 	if (!bcp->baudisabled) {
790 		stat->s_bau_disabled++;
791 		tm1 = get_cycles();
792 		for_each_present_cpu(tcpu) {
793 			tbcp = &per_cpu(bau_control, tcpu);
794 			if (tbcp->uvhub_master == hmaster) {
795 				tbcp->baudisabled = 1;
796 				tbcp->set_bau_on_time =
797 					tm1 + bcp->disabled_period;
798 			}
799 		}
800 	}
801 	spin_unlock(&hmaster->disable_lock);
802 }
803 
count_max_concurr(int stat,struct bau_control * bcp,struct bau_control * hmaster)804 static void count_max_concurr(int stat, struct bau_control *bcp,
805 				struct bau_control *hmaster)
806 {
807 	bcp->plugged_tries = 0;
808 	bcp->timeout_tries = 0;
809 	if (stat != FLUSH_COMPLETE)
810 		return;
811 	if (bcp->conseccompletes <= bcp->complete_threshold)
812 		return;
813 	if (hmaster->max_concurr >= hmaster->max_concurr_const)
814 		return;
815 	hmaster->max_concurr++;
816 }
817 
record_send_stats(cycles_t time1,cycles_t time2,struct bau_control * bcp,struct ptc_stats * stat,int completion_status,int try)818 static void record_send_stats(cycles_t time1, cycles_t time2,
819 		struct bau_control *bcp, struct ptc_stats *stat,
820 		int completion_status, int try)
821 {
822 	cycles_t elapsed;
823 
824 	if (time2 > time1) {
825 		elapsed = time2 - time1;
826 		stat->s_time += elapsed;
827 
828 		if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
829 			bcp->period_requests++;
830 			bcp->period_time += elapsed;
831 			if ((elapsed > usec_2_cycles(bcp->cong_response_us)) &&
832 			    (bcp->period_requests > bcp->cong_reps) &&
833 			    ((bcp->period_time / bcp->period_requests) >
834 					usec_2_cycles(bcp->cong_response_us))) {
835 				stat->s_congested++;
836 				disable_for_period(bcp, stat);
837 			}
838 		}
839 	} else
840 		stat->s_requestor--;
841 
842 	if (completion_status == FLUSH_COMPLETE && try > 1)
843 		stat->s_retriesok++;
844 	else if (completion_status == FLUSH_GIVEUP) {
845 		stat->s_giveup++;
846 		if (get_cycles() > bcp->period_end)
847 			bcp->period_giveups = 0;
848 		bcp->period_giveups++;
849 		if (bcp->period_giveups == 1)
850 			bcp->period_end = get_cycles() + bcp->disabled_period;
851 		if (bcp->period_giveups > bcp->giveup_limit) {
852 			disable_for_period(bcp, stat);
853 			stat->s_giveuplimit++;
854 		}
855 	}
856 }
857 
858 /*
859  * Because of a uv1 hardware bug only a limited number of concurrent
860  * requests can be made.
861  */
uv1_throttle(struct bau_control * hmaster,struct ptc_stats * stat)862 static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
863 {
864 	spinlock_t *lock = &hmaster->uvhub_lock;
865 	atomic_t *v;
866 
867 	v = &hmaster->active_descriptor_count;
868 	if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
869 		stat->s_throttles++;
870 		do {
871 			cpu_relax();
872 		} while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
873 	}
874 }
875 
876 /*
877  * Handle the completion status of a message send.
878  */
handle_cmplt(int completion_status,struct bau_desc * bau_desc,struct bau_control * bcp,struct bau_control * hmaster,struct ptc_stats * stat)879 static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
880 			struct bau_control *bcp, struct bau_control *hmaster,
881 			struct ptc_stats *stat)
882 {
883 	if (completion_status == FLUSH_RETRY_PLUGGED)
884 		destination_plugged(bau_desc, bcp, hmaster, stat);
885 	else if (completion_status == FLUSH_RETRY_TIMEOUT)
886 		destination_timeout(bau_desc, bcp, hmaster, stat);
887 }
888 
889 /*
890  * Send a broadcast and wait for it to complete.
891  *
892  * The flush_mask contains the cpus the broadcast is to be sent to including
893  * cpus that are on the local uvhub.
894  *
895  * Returns 0 if all flushing represented in the mask was done.
896  * Returns 1 if it gives up entirely and the original cpu mask is to be
897  * returned to the kernel.
898  */
uv_flush_send_and_wait(struct cpumask * flush_mask,struct bau_control * bcp,struct bau_desc * bau_desc)899 static int uv_flush_send_and_wait(struct cpumask *flush_mask,
900 				  struct bau_control *bcp,
901 				  struct bau_desc *bau_desc)
902 {
903 	int seq_number = 0;
904 	int completion_stat = 0;
905 	int uv1 = 0;
906 	long try = 0;
907 	unsigned long index;
908 	cycles_t time1;
909 	cycles_t time2;
910 	struct ptc_stats *stat = bcp->statp;
911 	struct bau_control *hmaster = bcp->uvhub_master;
912 	struct uv1_bau_msg_header *uv1_hdr = NULL;
913 	struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
914 
915 	if (bcp->uvhub_version == UV_BAU_V1) {
916 		uv1 = 1;
917 		uv1_throttle(hmaster, stat);
918 	}
919 
920 	while (hmaster->uvhub_quiesce)
921 		cpu_relax();
922 
923 	time1 = get_cycles();
924 	if (uv1)
925 		uv1_hdr = &bau_desc->header.uv1_hdr;
926 	else
927 		/* uv2 and uv3 */
928 		uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
929 
930 	do {
931 		if (try == 0) {
932 			if (uv1)
933 				uv1_hdr->msg_type = MSG_REGULAR;
934 			else
935 				uv2_3_hdr->msg_type = MSG_REGULAR;
936 			seq_number = bcp->message_number++;
937 		} else {
938 			if (uv1)
939 				uv1_hdr->msg_type = MSG_RETRY;
940 			else
941 				uv2_3_hdr->msg_type = MSG_RETRY;
942 			stat->s_retry_messages++;
943 		}
944 
945 		if (uv1)
946 			uv1_hdr->sequence = seq_number;
947 		else
948 			uv2_3_hdr->sequence = seq_number;
949 		index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
950 		bcp->send_message = get_cycles();
951 
952 		write_mmr_activation(index);
953 
954 		try++;
955 		completion_stat = ops.wait_completion(bau_desc, bcp, try);
956 
957 		handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
958 
959 		if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
960 			bcp->ipi_attempts = 0;
961 			stat->s_overipilimit++;
962 			completion_stat = FLUSH_GIVEUP;
963 			break;
964 		}
965 		cpu_relax();
966 	} while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
967 		 (completion_stat == FLUSH_RETRY_TIMEOUT));
968 
969 	time2 = get_cycles();
970 
971 	count_max_concurr(completion_stat, bcp, hmaster);
972 
973 	while (hmaster->uvhub_quiesce)
974 		cpu_relax();
975 
976 	atomic_dec(&hmaster->active_descriptor_count);
977 
978 	record_send_stats(time1, time2, bcp, stat, completion_stat, try);
979 
980 	if (completion_stat == FLUSH_GIVEUP)
981 		/* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
982 		return 1;
983 	return 0;
984 }
985 
986 /*
987  * The BAU is disabled for this uvhub. When the disabled time period has
988  * expired re-enable it.
989  * Return 0 if it is re-enabled for all cpus on this uvhub.
990  */
check_enable(struct bau_control * bcp,struct ptc_stats * stat)991 static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
992 {
993 	int tcpu;
994 	struct bau_control *tbcp;
995 	struct bau_control *hmaster;
996 
997 	hmaster = bcp->uvhub_master;
998 	spin_lock(&hmaster->disable_lock);
999 	if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
1000 		stat->s_bau_reenabled++;
1001 		for_each_present_cpu(tcpu) {
1002 			tbcp = &per_cpu(bau_control, tcpu);
1003 			if (tbcp->uvhub_master == hmaster) {
1004 				tbcp->baudisabled = 0;
1005 				tbcp->period_requests = 0;
1006 				tbcp->period_time = 0;
1007 				tbcp->period_giveups = 0;
1008 			}
1009 		}
1010 		spin_unlock(&hmaster->disable_lock);
1011 		return 0;
1012 	}
1013 	spin_unlock(&hmaster->disable_lock);
1014 	return -1;
1015 }
1016 
record_send_statistics(struct ptc_stats * stat,int locals,int hubs,int remotes,struct bau_desc * bau_desc)1017 static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
1018 				int remotes, struct bau_desc *bau_desc)
1019 {
1020 	stat->s_requestor++;
1021 	stat->s_ntargcpu += remotes + locals;
1022 	stat->s_ntargremotes += remotes;
1023 	stat->s_ntarglocals += locals;
1024 
1025 	/* uvhub statistics */
1026 	hubs = bau_uvhub_weight(&bau_desc->distribution);
1027 	if (locals) {
1028 		stat->s_ntarglocaluvhub++;
1029 		stat->s_ntargremoteuvhub += (hubs - 1);
1030 	} else
1031 		stat->s_ntargremoteuvhub += hubs;
1032 
1033 	stat->s_ntarguvhub += hubs;
1034 
1035 	if (hubs >= 16)
1036 		stat->s_ntarguvhub16++;
1037 	else if (hubs >= 8)
1038 		stat->s_ntarguvhub8++;
1039 	else if (hubs >= 4)
1040 		stat->s_ntarguvhub4++;
1041 	else if (hubs >= 2)
1042 		stat->s_ntarguvhub2++;
1043 	else
1044 		stat->s_ntarguvhub1++;
1045 }
1046 
1047 /*
1048  * Translate a cpu mask to the uvhub distribution mask in the BAU
1049  * activation descriptor.
1050  */
set_distrib_bits(struct cpumask * flush_mask,struct bau_control * bcp,struct bau_desc * bau_desc,int * localsp,int * remotesp)1051 static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1052 			struct bau_desc *bau_desc, int *localsp, int *remotesp)
1053 {
1054 	int cpu;
1055 	int pnode;
1056 	int cnt = 0;
1057 	struct hub_and_pnode *hpp;
1058 
1059 	for_each_cpu(cpu, flush_mask) {
1060 		/*
1061 		 * The distribution vector is a bit map of pnodes, relative
1062 		 * to the partition base pnode (and the partition base nasid
1063 		 * in the header).
1064 		 * Translate cpu to pnode and hub using a local memory array.
1065 		 */
1066 		hpp = &bcp->socket_master->thp[cpu];
1067 		pnode = hpp->pnode - bcp->partition_base_pnode;
1068 		bau_uvhub_set(pnode, &bau_desc->distribution);
1069 		cnt++;
1070 		if (hpp->uvhub == bcp->uvhub)
1071 			(*localsp)++;
1072 		else
1073 			(*remotesp)++;
1074 	}
1075 	if (!cnt)
1076 		return 1;
1077 	return 0;
1078 }
1079 
1080 /*
1081  * globally purge translation cache of a virtual address or all TLB's
1082  * @cpumask: mask of all cpu's in which the address is to be removed
1083  * @mm: mm_struct containing virtual address range
1084  * @start: start virtual address to be removed from TLB
1085  * @end: end virtual address to be remove from TLB
1086  * @cpu: the current cpu
1087  *
1088  * This is the entry point for initiating any UV global TLB shootdown.
1089  *
1090  * Purges the translation caches of all specified processors of the given
1091  * virtual address, or purges all TLB's on specified processors.
1092  *
1093  * The caller has derived the cpumask from the mm_struct.  This function
1094  * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1095  *
1096  * The cpumask is converted into a uvhubmask of the uvhubs containing
1097  * those cpus.
1098  *
1099  * Note that this function should be called with preemption disabled.
1100  *
1101  * Returns NULL if all remote flushing was done.
1102  * Returns pointer to cpumask if some remote flushing remains to be
1103  * done.  The returned pointer is valid till preemption is re-enabled.
1104  */
uv_flush_tlb_others(const struct cpumask * cpumask,const struct flush_tlb_info * info)1105 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
1106 					  const struct flush_tlb_info *info)
1107 {
1108 	unsigned int cpu = smp_processor_id();
1109 	int locals = 0, remotes = 0, hubs = 0;
1110 	struct bau_desc *bau_desc;
1111 	struct cpumask *flush_mask;
1112 	struct ptc_stats *stat;
1113 	struct bau_control *bcp;
1114 	unsigned long descriptor_status, status, address;
1115 
1116 	bcp = &per_cpu(bau_control, cpu);
1117 
1118 	if (bcp->nobau)
1119 		return cpumask;
1120 
1121 	stat = bcp->statp;
1122 	stat->s_enters++;
1123 
1124 	if (bcp->busy) {
1125 		descriptor_status =
1126 			read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1127 		status = ((descriptor_status >> (bcp->uvhub_cpu *
1128 			UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1129 		if (status == UV2H_DESC_BUSY)
1130 			return cpumask;
1131 		bcp->busy = 0;
1132 	}
1133 
1134 	/* bau was disabled due to slow response */
1135 	if (bcp->baudisabled) {
1136 		if (check_enable(bcp, stat)) {
1137 			stat->s_ipifordisabled++;
1138 			return cpumask;
1139 		}
1140 	}
1141 
1142 	/*
1143 	 * Each sending cpu has a per-cpu mask which it fills from the caller's
1144 	 * cpu mask.  All cpus are converted to uvhubs and copied to the
1145 	 * activation descriptor.
1146 	 */
1147 	flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
1148 	/* don't actually do a shootdown of the local cpu */
1149 	cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
1150 
1151 	if (cpumask_test_cpu(cpu, cpumask))
1152 		stat->s_ntargself++;
1153 
1154 	bau_desc = bcp->descriptor_base;
1155 	bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
1156 	bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
1157 	if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
1158 		return NULL;
1159 
1160 	record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1161 
1162 	if (!info->end || (info->end - info->start) <= PAGE_SIZE)
1163 		address = info->start;
1164 	else
1165 		address = TLB_FLUSH_ALL;
1166 
1167 	switch (bcp->uvhub_version) {
1168 	case UV_BAU_V1:
1169 	case UV_BAU_V2:
1170 	case UV_BAU_V3:
1171 		bau_desc->payload.uv1_2_3.address = address;
1172 		bau_desc->payload.uv1_2_3.sending_cpu = cpu;
1173 		break;
1174 	case UV_BAU_V4:
1175 		bau_desc->payload.uv4.address = address;
1176 		bau_desc->payload.uv4.sending_cpu = cpu;
1177 		bau_desc->payload.uv4.qualifier = BAU_DESC_QUALIFIER;
1178 		break;
1179 	}
1180 
1181 	/*
1182 	 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1183 	 * or 1 if it gave up and the original cpumask should be returned.
1184 	 */
1185 	if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
1186 		return NULL;
1187 	else
1188 		return cpumask;
1189 }
1190 
1191 /*
1192  * Search the message queue for any 'other' unprocessed message with the
1193  * same software acknowledge resource bit vector as the 'msg' message.
1194  */
find_another_by_swack(struct bau_pq_entry * msg,struct bau_control * bcp)1195 static struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
1196 						  struct bau_control *bcp)
1197 {
1198 	struct bau_pq_entry *msg_next = msg + 1;
1199 	unsigned char swack_vec = msg->swack_vec;
1200 
1201 	if (msg_next > bcp->queue_last)
1202 		msg_next = bcp->queue_first;
1203 	while (msg_next != msg) {
1204 		if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1205 				(msg_next->swack_vec == swack_vec))
1206 			return msg_next;
1207 		msg_next++;
1208 		if (msg_next > bcp->queue_last)
1209 			msg_next = bcp->queue_first;
1210 	}
1211 	return NULL;
1212 }
1213 
1214 /*
1215  * UV2 needs to work around a bug in which an arriving message has not
1216  * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1217  * Such a message must be ignored.
1218  */
process_uv2_message(struct msg_desc * mdp,struct bau_control * bcp)1219 static void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1220 {
1221 	unsigned long mmr_image;
1222 	unsigned char swack_vec;
1223 	struct bau_pq_entry *msg = mdp->msg;
1224 	struct bau_pq_entry *other_msg;
1225 
1226 	mmr_image = ops.read_l_sw_ack();
1227 	swack_vec = msg->swack_vec;
1228 
1229 	if ((swack_vec & mmr_image) == 0) {
1230 		/*
1231 		 * This message was assigned a swack resource, but no
1232 		 * reserved acknowlegment is pending.
1233 		 * The bug has prevented this message from setting the MMR.
1234 		 */
1235 		/*
1236 		 * Some message has set the MMR 'pending' bit; it might have
1237 		 * been another message.  Look for that message.
1238 		 */
1239 		other_msg = find_another_by_swack(msg, bcp);
1240 		if (other_msg) {
1241 			/*
1242 			 * There is another. Process this one but do not
1243 			 * ack it.
1244 			 */
1245 			bau_process_message(mdp, bcp, 0);
1246 			/*
1247 			 * Let the natural processing of that other message
1248 			 * acknowledge it. Don't get the processing of sw_ack's
1249 			 * out of order.
1250 			 */
1251 			return;
1252 		}
1253 	}
1254 
1255 	/*
1256 	 * Either the MMR shows this one pending a reply or there is no
1257 	 * other message using this sw_ack, so it is safe to acknowledge it.
1258 	 */
1259 	bau_process_message(mdp, bcp, 1);
1260 
1261 	return;
1262 }
1263 
1264 /*
1265  * The BAU message interrupt comes here. (registered by set_intr_gate)
1266  * See entry_64.S
1267  *
1268  * We received a broadcast assist message.
1269  *
1270  * Interrupts are disabled; this interrupt could represent
1271  * the receipt of several messages.
1272  *
1273  * All cores/threads on this hub get this interrupt.
1274  * The last one to see it does the software ack.
1275  * (the resource will not be freed until noninterruptable cpus see this
1276  *  interrupt; hardware may timeout the s/w ack and reply ERROR)
1277  */
uv_bau_message_interrupt(struct pt_regs * regs)1278 void uv_bau_message_interrupt(struct pt_regs *regs)
1279 {
1280 	int count = 0;
1281 	cycles_t time_start;
1282 	struct bau_pq_entry *msg;
1283 	struct bau_control *bcp;
1284 	struct ptc_stats *stat;
1285 	struct msg_desc msgdesc;
1286 
1287 	ack_APIC_irq();
1288 	kvm_set_cpu_l1tf_flush_l1d();
1289 	time_start = get_cycles();
1290 
1291 	bcp = &per_cpu(bau_control, smp_processor_id());
1292 	stat = bcp->statp;
1293 
1294 	msgdesc.queue_first = bcp->queue_first;
1295 	msgdesc.queue_last = bcp->queue_last;
1296 
1297 	msg = bcp->bau_msg_head;
1298 	while (msg->swack_vec) {
1299 		count++;
1300 
1301 		msgdesc.msg_slot = msg - msgdesc.queue_first;
1302 		msgdesc.msg = msg;
1303 		if (bcp->uvhub_version == UV_BAU_V2)
1304 			process_uv2_message(&msgdesc, bcp);
1305 		else
1306 			/* no error workaround for uv1 or uv3 */
1307 			bau_process_message(&msgdesc, bcp, 1);
1308 
1309 		msg++;
1310 		if (msg > msgdesc.queue_last)
1311 			msg = msgdesc.queue_first;
1312 		bcp->bau_msg_head = msg;
1313 	}
1314 	stat->d_time += (get_cycles() - time_start);
1315 	if (!count)
1316 		stat->d_nomsg++;
1317 	else if (count > 1)
1318 		stat->d_multmsg++;
1319 }
1320 
1321 /*
1322  * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
1323  * shootdown message timeouts enabled.  The timeout does not cause
1324  * an interrupt, but causes an error message to be returned to
1325  * the sender.
1326  */
enable_timeouts(void)1327 static void __init enable_timeouts(void)
1328 {
1329 	int uvhub;
1330 	int nuvhubs;
1331 	int pnode;
1332 	unsigned long mmr_image;
1333 
1334 	nuvhubs = uv_num_possible_blades();
1335 
1336 	for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1337 		if (!uv_blade_nr_possible_cpus(uvhub))
1338 			continue;
1339 
1340 		pnode = uv_blade_to_pnode(uvhub);
1341 		mmr_image = read_mmr_misc_control(pnode);
1342 		/*
1343 		 * Set the timeout period and then lock it in, in three
1344 		 * steps; captures and locks in the period.
1345 		 *
1346 		 * To program the period, the SOFT_ACK_MODE must be off.
1347 		 */
1348 		mmr_image &= ~(1L << SOFTACK_MSHIFT);
1349 		write_mmr_misc_control(pnode, mmr_image);
1350 		/*
1351 		 * Set the 4-bit period.
1352 		 */
1353 		mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1354 		mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1355 		write_mmr_misc_control(pnode, mmr_image);
1356 		/*
1357 		 * UV1:
1358 		 * Subsequent reversals of the timebase bit (3) cause an
1359 		 * immediate timeout of one or all INTD resources as
1360 		 * indicated in bits 2:0 (7 causes all of them to timeout).
1361 		 */
1362 		mmr_image |= (1L << SOFTACK_MSHIFT);
1363 		if (is_uv2_hub()) {
1364 			/* do not touch the legacy mode bit */
1365 			/* hw bug workaround; do not use extended status */
1366 			mmr_image &= ~(1L << UV2_EXT_SHFT);
1367 		} else if (is_uv3_hub()) {
1368 			mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
1369 			mmr_image |= (1L << SB_STATUS_SHFT);
1370 		}
1371 		write_mmr_misc_control(pnode, mmr_image);
1372 	}
1373 }
1374 
ptc_seq_start(struct seq_file * file,loff_t * offset)1375 static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1376 {
1377 	if (*offset < num_possible_cpus())
1378 		return offset;
1379 	return NULL;
1380 }
1381 
ptc_seq_next(struct seq_file * file,void * data,loff_t * offset)1382 static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1383 {
1384 	(*offset)++;
1385 	if (*offset < num_possible_cpus())
1386 		return offset;
1387 	return NULL;
1388 }
1389 
ptc_seq_stop(struct seq_file * file,void * data)1390 static void ptc_seq_stop(struct seq_file *file, void *data)
1391 {
1392 }
1393 
1394 /*
1395  * Display the statistics thru /proc/sgi_uv/ptc_statistics
1396  * 'data' points to the cpu number
1397  * Note: see the descriptions in stat_description[].
1398  */
ptc_seq_show(struct seq_file * file,void * data)1399 static int ptc_seq_show(struct seq_file *file, void *data)
1400 {
1401 	struct ptc_stats *stat;
1402 	struct bau_control *bcp;
1403 	int cpu;
1404 
1405 	cpu = *(loff_t *)data;
1406 	if (!cpu) {
1407 		seq_puts(file,
1408 			 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
1409 		seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1410 		seq_puts(file,
1411 			 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1412 		seq_puts(file,
1413 			 "rok resetp resett giveup sto bz throt disable ");
1414 		seq_puts(file,
1415 			 "enable wars warshw warwaits enters ipidis plugged ");
1416 		seq_puts(file,
1417 			 "ipiover glim cong swack recv rtime all one mult ");
1418 		seq_puts(file, "none retry canc nocan reset rcan\n");
1419 	}
1420 	if (cpu < num_possible_cpus() && cpu_online(cpu)) {
1421 		bcp = &per_cpu(bau_control, cpu);
1422 		if (bcp->nobau) {
1423 			seq_printf(file, "cpu %d bau disabled\n", cpu);
1424 			return 0;
1425 		}
1426 		stat = bcp->statp;
1427 		/* source side statistics */
1428 		seq_printf(file,
1429 			"cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1430 			   cpu, bcp->nobau, stat->s_requestor,
1431 			   cycles_2_us(stat->s_time),
1432 			   stat->s_ntargself, stat->s_ntarglocals,
1433 			   stat->s_ntargremotes, stat->s_ntargcpu,
1434 			   stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1435 			   stat->s_ntarguvhub, stat->s_ntarguvhub16);
1436 		seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
1437 			   stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1438 			   stat->s_ntarguvhub2, stat->s_ntarguvhub1,
1439 			   stat->s_dtimeout, stat->s_strongnacks);
1440 		seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
1441 			   stat->s_retry_messages, stat->s_retriesok,
1442 			   stat->s_resets_plug, stat->s_resets_timeout,
1443 			   stat->s_giveup, stat->s_stimeout,
1444 			   stat->s_busy, stat->s_throttles);
1445 		seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1446 			   stat->s_bau_disabled, stat->s_bau_reenabled,
1447 			   stat->s_uv2_wars, stat->s_uv2_wars_hw,
1448 			   stat->s_uv2_war_waits, stat->s_enters,
1449 			   stat->s_ipifordisabled, stat->s_plugged,
1450 			   stat->s_overipilimit, stat->s_giveuplimit,
1451 			   stat->s_congested);
1452 
1453 		/* destination side statistics */
1454 		seq_printf(file,
1455 			"%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
1456 			   ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)),
1457 			   stat->d_requestee, cycles_2_us(stat->d_time),
1458 			   stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1459 			   stat->d_nomsg, stat->d_retries, stat->d_canceled,
1460 			   stat->d_nocanceled, stat->d_resets,
1461 			   stat->d_rcanceled);
1462 	}
1463 	return 0;
1464 }
1465 
1466 /*
1467  * Display the tunables thru debugfs
1468  */
tunables_read(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)1469 static ssize_t tunables_read(struct file *file, char __user *userbuf,
1470 				size_t count, loff_t *ppos)
1471 {
1472 	char *buf;
1473 	int ret;
1474 
1475 	buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1476 		"max_concur plugged_delay plugsb4reset timeoutsb4reset",
1477 		"ipi_reset_limit complete_threshold congested_response_us",
1478 		"congested_reps disabled_period giveup_limit",
1479 		max_concurr, plugged_delay, plugsb4reset,
1480 		timeoutsb4reset, ipi_reset_limit, complete_threshold,
1481 		congested_respns_us, congested_reps, disabled_period,
1482 		giveup_limit);
1483 
1484 	if (!buf)
1485 		return -ENOMEM;
1486 
1487 	ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1488 	kfree(buf);
1489 	return ret;
1490 }
1491 
1492 /*
1493  * handle a write to /proc/sgi_uv/ptc_statistics
1494  * -1: reset the statistics
1495  *  0: display meaning of the statistics
1496  */
ptc_proc_write(struct file * file,const char __user * user,size_t count,loff_t * data)1497 static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1498 				size_t count, loff_t *data)
1499 {
1500 	int cpu;
1501 	int i;
1502 	int elements;
1503 	long input_arg;
1504 	char optstr[64];
1505 	struct ptc_stats *stat;
1506 
1507 	if (count == 0 || count > sizeof(optstr))
1508 		return -EINVAL;
1509 	if (copy_from_user(optstr, user, count))
1510 		return -EFAULT;
1511 	optstr[count - 1] = '\0';
1512 
1513 	if (!strcmp(optstr, "on")) {
1514 		set_bau_on();
1515 		return count;
1516 	} else if (!strcmp(optstr, "off")) {
1517 		set_bau_off();
1518 		return count;
1519 	}
1520 
1521 	if (kstrtol(optstr, 10, &input_arg) < 0) {
1522 		pr_debug("%s is invalid\n", optstr);
1523 		return -EINVAL;
1524 	}
1525 
1526 	if (input_arg == 0) {
1527 		elements = ARRAY_SIZE(stat_description);
1528 		pr_debug("# cpu:      cpu number\n");
1529 		pr_debug("Sender statistics:\n");
1530 		for (i = 0; i < elements; i++)
1531 			pr_debug("%s\n", stat_description[i]);
1532 	} else if (input_arg == -1) {
1533 		for_each_present_cpu(cpu) {
1534 			stat = &per_cpu(ptcstats, cpu);
1535 			memset(stat, 0, sizeof(struct ptc_stats));
1536 		}
1537 	}
1538 
1539 	return count;
1540 }
1541 
local_atoi(const char * name)1542 static int local_atoi(const char *name)
1543 {
1544 	int val = 0;
1545 
1546 	for (;; name++) {
1547 		switch (*name) {
1548 		case '0' ... '9':
1549 			val = 10*val+(*name-'0');
1550 			break;
1551 		default:
1552 			return val;
1553 		}
1554 	}
1555 }
1556 
1557 /*
1558  * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1559  * Zero values reset them to defaults.
1560  */
parse_tunables_write(struct bau_control * bcp,char * instr,int count)1561 static int parse_tunables_write(struct bau_control *bcp, char *instr,
1562 				int count)
1563 {
1564 	char *p;
1565 	char *q;
1566 	int cnt = 0;
1567 	int val;
1568 	int e = ARRAY_SIZE(tunables);
1569 
1570 	p = instr + strspn(instr, WHITESPACE);
1571 	q = p;
1572 	for (; *p; p = q + strspn(q, WHITESPACE)) {
1573 		q = p + strcspn(p, WHITESPACE);
1574 		cnt++;
1575 		if (q == p)
1576 			break;
1577 	}
1578 	if (cnt != e) {
1579 		pr_info("bau tunable error: should be %d values\n", e);
1580 		return -EINVAL;
1581 	}
1582 
1583 	p = instr + strspn(instr, WHITESPACE);
1584 	q = p;
1585 	for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1586 		q = p + strcspn(p, WHITESPACE);
1587 		val = local_atoi(p);
1588 		switch (cnt) {
1589 		case 0:
1590 			if (val == 0) {
1591 				max_concurr = MAX_BAU_CONCURRENT;
1592 				max_concurr_const = MAX_BAU_CONCURRENT;
1593 				continue;
1594 			}
1595 			if (val < 1 || val > bcp->cpus_in_uvhub) {
1596 				pr_debug(
1597 				"Error: BAU max concurrent %d is invalid\n",
1598 				val);
1599 				return -EINVAL;
1600 			}
1601 			max_concurr = val;
1602 			max_concurr_const = val;
1603 			continue;
1604 		default:
1605 			if (val == 0)
1606 				*tunables[cnt].tunp = tunables[cnt].deflt;
1607 			else
1608 				*tunables[cnt].tunp = val;
1609 			continue;
1610 		}
1611 	}
1612 	return 0;
1613 }
1614 
1615 /*
1616  * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1617  */
tunables_write(struct file * file,const char __user * user,size_t count,loff_t * data)1618 static ssize_t tunables_write(struct file *file, const char __user *user,
1619 				size_t count, loff_t *data)
1620 {
1621 	int cpu;
1622 	int ret;
1623 	char instr[100];
1624 	struct bau_control *bcp;
1625 
1626 	if (count == 0 || count > sizeof(instr)-1)
1627 		return -EINVAL;
1628 	if (copy_from_user(instr, user, count))
1629 		return -EFAULT;
1630 
1631 	instr[count] = '\0';
1632 
1633 	cpu = get_cpu();
1634 	bcp = &per_cpu(bau_control, cpu);
1635 	ret = parse_tunables_write(bcp, instr, count);
1636 	put_cpu();
1637 	if (ret)
1638 		return ret;
1639 
1640 	for_each_present_cpu(cpu) {
1641 		bcp = &per_cpu(bau_control, cpu);
1642 		bcp->max_concurr         = max_concurr;
1643 		bcp->max_concurr_const   = max_concurr;
1644 		bcp->plugged_delay       = plugged_delay;
1645 		bcp->plugsb4reset        = plugsb4reset;
1646 		bcp->timeoutsb4reset     = timeoutsb4reset;
1647 		bcp->ipi_reset_limit     = ipi_reset_limit;
1648 		bcp->complete_threshold  = complete_threshold;
1649 		bcp->cong_response_us    = congested_respns_us;
1650 		bcp->cong_reps           = congested_reps;
1651 		bcp->disabled_period     = sec_2_cycles(disabled_period);
1652 		bcp->giveup_limit        = giveup_limit;
1653 	}
1654 	return count;
1655 }
1656 
1657 static const struct seq_operations uv_ptc_seq_ops = {
1658 	.start		= ptc_seq_start,
1659 	.next		= ptc_seq_next,
1660 	.stop		= ptc_seq_stop,
1661 	.show		= ptc_seq_show
1662 };
1663 
ptc_proc_open(struct inode * inode,struct file * file)1664 static int ptc_proc_open(struct inode *inode, struct file *file)
1665 {
1666 	return seq_open(file, &uv_ptc_seq_ops);
1667 }
1668 
tunables_open(struct inode * inode,struct file * file)1669 static int tunables_open(struct inode *inode, struct file *file)
1670 {
1671 	return 0;
1672 }
1673 
1674 static const struct file_operations proc_uv_ptc_operations = {
1675 	.open		= ptc_proc_open,
1676 	.read		= seq_read,
1677 	.write		= ptc_proc_write,
1678 	.llseek		= seq_lseek,
1679 	.release	= seq_release,
1680 };
1681 
1682 static const struct file_operations tunables_fops = {
1683 	.open		= tunables_open,
1684 	.read		= tunables_read,
1685 	.write		= tunables_write,
1686 	.llseek		= default_llseek,
1687 };
1688 
uv_ptc_init(void)1689 static int __init uv_ptc_init(void)
1690 {
1691 	struct proc_dir_entry *proc_uv_ptc;
1692 
1693 	if (!is_uv_system())
1694 		return 0;
1695 
1696 	proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1697 				  &proc_uv_ptc_operations);
1698 	if (!proc_uv_ptc) {
1699 		pr_err("unable to create %s proc entry\n",
1700 		       UV_PTC_BASENAME);
1701 		return -EINVAL;
1702 	}
1703 
1704 	tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1705 	if (!tunables_dir) {
1706 		pr_err("unable to create debugfs directory %s\n",
1707 		       UV_BAU_TUNABLES_DIR);
1708 		return -EINVAL;
1709 	}
1710 	tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
1711 					tunables_dir, NULL, &tunables_fops);
1712 	if (!tunables_file) {
1713 		pr_err("unable to create debugfs file %s\n",
1714 		       UV_BAU_TUNABLES_FILE);
1715 		return -EINVAL;
1716 	}
1717 	return 0;
1718 }
1719 
1720 /*
1721  * Initialize the sending side's sending buffers.
1722  */
activation_descriptor_init(int node,int pnode,int base_pnode)1723 static void activation_descriptor_init(int node, int pnode, int base_pnode)
1724 {
1725 	int i;
1726 	int cpu;
1727 	int uv1 = 0;
1728 	unsigned long gpa;
1729 	unsigned long m;
1730 	unsigned long n;
1731 	size_t dsize;
1732 	struct bau_desc *bau_desc;
1733 	struct bau_desc *bd2;
1734 	struct uv1_bau_msg_header *uv1_hdr;
1735 	struct uv2_3_bau_msg_header *uv2_3_hdr;
1736 	struct bau_control *bcp;
1737 
1738 	/*
1739 	 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1740 	 * per cpu; and one per cpu on the uvhub (ADP_SZ)
1741 	 */
1742 	dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1743 	bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
1744 	BUG_ON(!bau_desc);
1745 
1746 	gpa = uv_gpa(bau_desc);
1747 	n = uv_gpa_to_gnode(gpa);
1748 	m = ops.bau_gpa_to_offset(gpa);
1749 	if (is_uv1_hub())
1750 		uv1 = 1;
1751 
1752 	/* the 14-bit pnode */
1753 	write_mmr_descriptor_base(pnode,
1754 		(n << UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT | m));
1755 	/*
1756 	 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
1757 	 * cpu even though we only use the first one; one descriptor can
1758 	 * describe a broadcast to 256 uv hubs.
1759 	 */
1760 	for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
1761 		memset(bd2, 0, sizeof(struct bau_desc));
1762 		if (uv1) {
1763 			uv1_hdr = &bd2->header.uv1_hdr;
1764 			uv1_hdr->swack_flag = 1;
1765 			/*
1766 			 * The base_dest_nasid set in the message header
1767 			 * is the nasid of the first uvhub in the partition.
1768 			 * The bit map will indicate destination pnode numbers
1769 			 * relative to that base. They may not be consecutive
1770 			 * if nasid striding is being used.
1771 			 */
1772 			uv1_hdr->base_dest_nasid =
1773 			                          UV_PNODE_TO_NASID(base_pnode);
1774 			uv1_hdr->dest_subnodeid  = UV_LB_SUBNODEID;
1775 			uv1_hdr->command         = UV_NET_ENDPOINT_INTD;
1776 			uv1_hdr->int_both        = 1;
1777 			/*
1778 			 * all others need to be set to zero:
1779 			 *   fairness chaining multilevel count replied_to
1780 			 */
1781 		} else {
1782 			/*
1783 			 * BIOS uses legacy mode, but uv2 and uv3 hardware always
1784 			 * uses native mode for selective broadcasts.
1785 			 */
1786 			uv2_3_hdr = &bd2->header.uv2_3_hdr;
1787 			uv2_3_hdr->swack_flag      = 1;
1788 			uv2_3_hdr->base_dest_nasid =
1789 			                          UV_PNODE_TO_NASID(base_pnode);
1790 			uv2_3_hdr->dest_subnodeid  = UV_LB_SUBNODEID;
1791 			uv2_3_hdr->command         = UV_NET_ENDPOINT_INTD;
1792 		}
1793 	}
1794 	for_each_present_cpu(cpu) {
1795 		if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1796 			continue;
1797 		bcp = &per_cpu(bau_control, cpu);
1798 		bcp->descriptor_base = bau_desc;
1799 	}
1800 }
1801 
1802 /*
1803  * initialize the destination side's receiving buffers
1804  * entered for each uvhub in the partition
1805  * - node is first node (kernel memory notion) on the uvhub
1806  * - pnode is the uvhub's physical identifier
1807  */
pq_init(int node,int pnode)1808 static void pq_init(int node, int pnode)
1809 {
1810 	int cpu;
1811 	size_t plsize;
1812 	char *cp;
1813 	void *vp;
1814 	unsigned long gnode, first, last, tail;
1815 	struct bau_pq_entry *pqp;
1816 	struct bau_control *bcp;
1817 
1818 	plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1819 	vp = kmalloc_node(plsize, GFP_KERNEL, node);
1820 	pqp = (struct bau_pq_entry *)vp;
1821 	BUG_ON(!pqp);
1822 
1823 	cp = (char *)pqp + 31;
1824 	pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
1825 
1826 	for_each_present_cpu(cpu) {
1827 		if (pnode != uv_cpu_to_pnode(cpu))
1828 			continue;
1829 		/* for every cpu on this pnode: */
1830 		bcp = &per_cpu(bau_control, cpu);
1831 		bcp->queue_first	= pqp;
1832 		bcp->bau_msg_head	= pqp;
1833 		bcp->queue_last		= pqp + (DEST_Q_SIZE - 1);
1834 	}
1835 
1836 	first = ops.bau_gpa_to_offset(uv_gpa(pqp));
1837 	last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1)));
1838 
1839 	/*
1840 	 * Pre UV4, the gnode is required to locate the payload queue
1841 	 * and the payload queue tail must be maintained by the kernel.
1842 	 */
1843 	bcp = &per_cpu(bau_control, smp_processor_id());
1844 	if (bcp->uvhub_version <= UV_BAU_V3) {
1845 		tail = first;
1846 		gnode = uv_gpa_to_gnode(uv_gpa(pqp));
1847 		first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail;
1848 		write_mmr_payload_tail(pnode, tail);
1849 	}
1850 
1851 	ops.write_payload_first(pnode, first);
1852 	ops.write_payload_last(pnode, last);
1853 
1854 	/* in effect, all msg_type's are set to MSG_NOOP */
1855 	memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
1856 }
1857 
1858 /*
1859  * Initialization of each UV hub's structures
1860  */
init_uvhub(int uvhub,int vector,int base_pnode)1861 static void __init init_uvhub(int uvhub, int vector, int base_pnode)
1862 {
1863 	int node;
1864 	int pnode;
1865 	unsigned long apicid;
1866 
1867 	node = uvhub_to_first_node(uvhub);
1868 	pnode = uv_blade_to_pnode(uvhub);
1869 
1870 	activation_descriptor_init(node, pnode, base_pnode);
1871 
1872 	pq_init(node, pnode);
1873 	/*
1874 	 * The below initialization can't be in firmware because the
1875 	 * messaging IRQ will be determined by the OS.
1876 	 */
1877 	apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1878 	write_mmr_data_config(pnode, ((apicid << 32) | vector));
1879 }
1880 
1881 /*
1882  * We will set BAU_MISC_CONTROL with a timeout period.
1883  * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1884  * So the destination timeout period has to be calculated from them.
1885  */
calculate_destination_timeout(void)1886 static int calculate_destination_timeout(void)
1887 {
1888 	unsigned long mmr_image;
1889 	int mult1;
1890 	int mult2;
1891 	int index;
1892 	int base;
1893 	int ret;
1894 	unsigned long ts_ns;
1895 
1896 	if (is_uv1_hub()) {
1897 		mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
1898 		mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1899 		index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1900 		mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1901 		mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1902 		ts_ns = timeout_base_ns[index];
1903 		ts_ns *= (mult1 * mult2);
1904 		ret = ts_ns / 1000;
1905 	} else {
1906 		/* same destination timeout for uv2 and uv3 */
1907 		/* 4 bits  0/1 for 10/80us base, 3 bits of multiplier */
1908 		mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
1909 		mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1910 		if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
1911 			base = 80;
1912 		else
1913 			base = 10;
1914 		mult1 = mmr_image & UV2_ACK_MASK;
1915 		ret = mult1 * base;
1916 	}
1917 	return ret;
1918 }
1919 
init_per_cpu_tunables(void)1920 static void __init init_per_cpu_tunables(void)
1921 {
1922 	int cpu;
1923 	struct bau_control *bcp;
1924 
1925 	for_each_present_cpu(cpu) {
1926 		bcp = &per_cpu(bau_control, cpu);
1927 		bcp->baudisabled		= 0;
1928 		if (nobau)
1929 			bcp->nobau		= true;
1930 		bcp->statp			= &per_cpu(ptcstats, cpu);
1931 		/* time interval to catch a hardware stay-busy bug */
1932 		bcp->timeout_interval		= usec_2_cycles(2*timeout_us);
1933 		bcp->max_concurr		= max_concurr;
1934 		bcp->max_concurr_const		= max_concurr;
1935 		bcp->plugged_delay		= plugged_delay;
1936 		bcp->plugsb4reset		= plugsb4reset;
1937 		bcp->timeoutsb4reset		= timeoutsb4reset;
1938 		bcp->ipi_reset_limit		= ipi_reset_limit;
1939 		bcp->complete_threshold		= complete_threshold;
1940 		bcp->cong_response_us		= congested_respns_us;
1941 		bcp->cong_reps			= congested_reps;
1942 		bcp->disabled_period		= sec_2_cycles(disabled_period);
1943 		bcp->giveup_limit		= giveup_limit;
1944 		spin_lock_init(&bcp->queue_lock);
1945 		spin_lock_init(&bcp->uvhub_lock);
1946 		spin_lock_init(&bcp->disable_lock);
1947 	}
1948 }
1949 
1950 /*
1951  * Scan all cpus to collect blade and socket summaries.
1952  */
get_cpu_topology(int base_pnode,struct uvhub_desc * uvhub_descs,unsigned char * uvhub_mask)1953 static int __init get_cpu_topology(int base_pnode,
1954 					struct uvhub_desc *uvhub_descs,
1955 					unsigned char *uvhub_mask)
1956 {
1957 	int cpu;
1958 	int pnode;
1959 	int uvhub;
1960 	int socket;
1961 	struct bau_control *bcp;
1962 	struct uvhub_desc *bdp;
1963 	struct socket_desc *sdp;
1964 
1965 	for_each_present_cpu(cpu) {
1966 		bcp = &per_cpu(bau_control, cpu);
1967 
1968 		memset(bcp, 0, sizeof(struct bau_control));
1969 
1970 		pnode = uv_cpu_hub_info(cpu)->pnode;
1971 		if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
1972 			pr_emerg(
1973 				"cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1974 				cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
1975 			return 1;
1976 		}
1977 
1978 		bcp->osnode = cpu_to_node(cpu);
1979 		bcp->partition_base_pnode = base_pnode;
1980 
1981 		uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1982 		*(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1983 		bdp = &uvhub_descs[uvhub];
1984 
1985 		bdp->num_cpus++;
1986 		bdp->uvhub = uvhub;
1987 		bdp->pnode = pnode;
1988 
1989 		/* kludge: 'assuming' one node per socket, and assuming that
1990 		   disabling a socket just leaves a gap in node numbers */
1991 		socket = bcp->osnode & 1;
1992 		bdp->socket_mask |= (1 << socket);
1993 		sdp = &bdp->socket[socket];
1994 		sdp->cpu_number[sdp->num_cpus] = cpu;
1995 		sdp->num_cpus++;
1996 		if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1997 			pr_emerg("%d cpus per socket invalid\n",
1998 				sdp->num_cpus);
1999 			return 1;
2000 		}
2001 	}
2002 	return 0;
2003 }
2004 
2005 /*
2006  * Each socket is to get a local array of pnodes/hubs.
2007  */
make_per_cpu_thp(struct bau_control * smaster)2008 static void make_per_cpu_thp(struct bau_control *smaster)
2009 {
2010 	int cpu;
2011 	size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
2012 
2013 	smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
2014 	memset(smaster->thp, 0, hpsz);
2015 	for_each_present_cpu(cpu) {
2016 		smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
2017 		smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
2018 	}
2019 }
2020 
2021 /*
2022  * Each uvhub is to get a local cpumask.
2023  */
make_per_hub_cpumask(struct bau_control * hmaster)2024 static void make_per_hub_cpumask(struct bau_control *hmaster)
2025 {
2026 	int sz = sizeof(cpumask_t);
2027 
2028 	hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
2029 }
2030 
2031 /*
2032  * Initialize all the per_cpu information for the cpu's on a given socket,
2033  * given what has been gathered into the socket_desc struct.
2034  * And reports the chosen hub and socket masters back to the caller.
2035  */
scan_sock(struct socket_desc * sdp,struct uvhub_desc * bdp,struct bau_control ** smasterp,struct bau_control ** hmasterp)2036 static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
2037 			struct bau_control **smasterp,
2038 			struct bau_control **hmasterp)
2039 {
2040 	int i, cpu, uvhub_cpu;
2041 	struct bau_control *bcp;
2042 
2043 	for (i = 0; i < sdp->num_cpus; i++) {
2044 		cpu = sdp->cpu_number[i];
2045 		bcp = &per_cpu(bau_control, cpu);
2046 		bcp->cpu = cpu;
2047 		if (i == 0) {
2048 			*smasterp = bcp;
2049 			if (!(*hmasterp))
2050 				*hmasterp = bcp;
2051 		}
2052 		bcp->cpus_in_uvhub = bdp->num_cpus;
2053 		bcp->cpus_in_socket = sdp->num_cpus;
2054 		bcp->socket_master = *smasterp;
2055 		bcp->uvhub = bdp->uvhub;
2056 		if (is_uv1_hub())
2057 			bcp->uvhub_version = UV_BAU_V1;
2058 		else if (is_uv2_hub())
2059 			bcp->uvhub_version = UV_BAU_V2;
2060 		else if (is_uv3_hub())
2061 			bcp->uvhub_version = UV_BAU_V3;
2062 		else if (is_uv4_hub())
2063 			bcp->uvhub_version = UV_BAU_V4;
2064 		else {
2065 			pr_emerg("uvhub version not 1, 2, 3, or 4\n");
2066 			return 1;
2067 		}
2068 		bcp->uvhub_master = *hmasterp;
2069 		uvhub_cpu = uv_cpu_blade_processor_id(cpu);
2070 		bcp->uvhub_cpu = uvhub_cpu;
2071 
2072 		/*
2073 		 * The ERROR and BUSY status registers are located pairwise over
2074 		 * the STATUS_0 and STATUS_1 mmrs; each an array[32] of 2 bits.
2075 		 */
2076 		if (uvhub_cpu < UV_CPUS_PER_AS) {
2077 			bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
2078 			bcp->status_index = uvhub_cpu * UV_ACT_STATUS_SIZE;
2079 		} else {
2080 			bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
2081 			bcp->status_index = (uvhub_cpu - UV_CPUS_PER_AS)
2082 						* UV_ACT_STATUS_SIZE;
2083 		}
2084 
2085 		if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2086 			pr_emerg("%d cpus per uvhub invalid\n",
2087 				bcp->uvhub_cpu);
2088 			return 1;
2089 		}
2090 	}
2091 	return 0;
2092 }
2093 
2094 /*
2095  * Summarize the blade and socket topology into the per_cpu structures.
2096  */
summarize_uvhub_sockets(int nuvhubs,struct uvhub_desc * uvhub_descs,unsigned char * uvhub_mask)2097 static int __init summarize_uvhub_sockets(int nuvhubs,
2098 			struct uvhub_desc *uvhub_descs,
2099 			unsigned char *uvhub_mask)
2100 {
2101 	int socket;
2102 	int uvhub;
2103 	unsigned short socket_mask;
2104 
2105 	for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2106 		struct uvhub_desc *bdp;
2107 		struct bau_control *smaster = NULL;
2108 		struct bau_control *hmaster = NULL;
2109 
2110 		if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2111 			continue;
2112 
2113 		bdp = &uvhub_descs[uvhub];
2114 		socket_mask = bdp->socket_mask;
2115 		socket = 0;
2116 		while (socket_mask) {
2117 			struct socket_desc *sdp;
2118 			if ((socket_mask & 1)) {
2119 				sdp = &bdp->socket[socket];
2120 				if (scan_sock(sdp, bdp, &smaster, &hmaster))
2121 					return 1;
2122 				make_per_cpu_thp(smaster);
2123 			}
2124 			socket++;
2125 			socket_mask = (socket_mask >> 1);
2126 		}
2127 		make_per_hub_cpumask(hmaster);
2128 	}
2129 	return 0;
2130 }
2131 
2132 /*
2133  * initialize the bau_control structure for each cpu
2134  */
init_per_cpu(int nuvhubs,int base_part_pnode)2135 static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2136 {
2137 	unsigned char *uvhub_mask;
2138 	void *vp;
2139 	struct uvhub_desc *uvhub_descs;
2140 
2141 	if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2142 		timeout_us = calculate_destination_timeout();
2143 
2144 	vp = kmalloc_array(nuvhubs, sizeof(struct uvhub_desc), GFP_KERNEL);
2145 	uvhub_descs = (struct uvhub_desc *)vp;
2146 	memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
2147 	uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2148 
2149 	if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
2150 		goto fail;
2151 
2152 	if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
2153 		goto fail;
2154 
2155 	kfree(uvhub_descs);
2156 	kfree(uvhub_mask);
2157 	init_per_cpu_tunables();
2158 	return 0;
2159 
2160 fail:
2161 	kfree(uvhub_descs);
2162 	kfree(uvhub_mask);
2163 	return 1;
2164 }
2165 
2166 static const struct bau_operations uv1_bau_ops __initconst = {
2167 	.bau_gpa_to_offset       = uv_gpa_to_offset,
2168 	.read_l_sw_ack           = read_mmr_sw_ack,
2169 	.read_g_sw_ack           = read_gmmr_sw_ack,
2170 	.write_l_sw_ack          = write_mmr_sw_ack,
2171 	.write_g_sw_ack          = write_gmmr_sw_ack,
2172 	.write_payload_first     = write_mmr_payload_first,
2173 	.write_payload_last      = write_mmr_payload_last,
2174 	.wait_completion	 = uv1_wait_completion,
2175 };
2176 
2177 static const struct bau_operations uv2_3_bau_ops __initconst = {
2178 	.bau_gpa_to_offset       = uv_gpa_to_offset,
2179 	.read_l_sw_ack           = read_mmr_sw_ack,
2180 	.read_g_sw_ack           = read_gmmr_sw_ack,
2181 	.write_l_sw_ack          = write_mmr_sw_ack,
2182 	.write_g_sw_ack          = write_gmmr_sw_ack,
2183 	.write_payload_first     = write_mmr_payload_first,
2184 	.write_payload_last      = write_mmr_payload_last,
2185 	.wait_completion	 = uv2_3_wait_completion,
2186 };
2187 
2188 static const struct bau_operations uv4_bau_ops __initconst = {
2189 	.bau_gpa_to_offset       = uv_gpa_to_soc_phys_ram,
2190 	.read_l_sw_ack           = read_mmr_proc_sw_ack,
2191 	.read_g_sw_ack           = read_gmmr_proc_sw_ack,
2192 	.write_l_sw_ack          = write_mmr_proc_sw_ack,
2193 	.write_g_sw_ack          = write_gmmr_proc_sw_ack,
2194 	.write_payload_first     = write_mmr_proc_payload_first,
2195 	.write_payload_last      = write_mmr_proc_payload_last,
2196 	.wait_completion         = uv4_wait_completion,
2197 };
2198 
2199 /*
2200  * Initialization of BAU-related structures
2201  */
uv_bau_init(void)2202 static int __init uv_bau_init(void)
2203 {
2204 	int uvhub;
2205 	int pnode;
2206 	int nuvhubs;
2207 	int cur_cpu;
2208 	int cpus;
2209 	int vector;
2210 	cpumask_var_t *mask;
2211 
2212 	if (!is_uv_system())
2213 		return 0;
2214 
2215 	if (is_uv4_hub())
2216 		ops = uv4_bau_ops;
2217 	else if (is_uv3_hub())
2218 		ops = uv2_3_bau_ops;
2219 	else if (is_uv2_hub())
2220 		ops = uv2_3_bau_ops;
2221 	else if (is_uv1_hub())
2222 		ops = uv1_bau_ops;
2223 
2224 	nuvhubs = uv_num_possible_blades();
2225 	if (nuvhubs < 2) {
2226 		pr_crit("UV: BAU disabled - insufficient hub count\n");
2227 		goto err_bau_disable;
2228 	}
2229 
2230 	for_each_possible_cpu(cur_cpu) {
2231 		mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2232 		zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2233 	}
2234 
2235 	uv_base_pnode = 0x7fffffff;
2236 	for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2237 		cpus = uv_blade_nr_possible_cpus(uvhub);
2238 		if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2239 			uv_base_pnode = uv_blade_to_pnode(uvhub);
2240 	}
2241 
2242 	/* software timeouts are not supported on UV4 */
2243 	if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2244 		enable_timeouts();
2245 
2246 	if (init_per_cpu(nuvhubs, uv_base_pnode)) {
2247 		pr_crit("UV: BAU disabled - per CPU init failed\n");
2248 		goto err_bau_disable;
2249 	}
2250 
2251 	vector = UV_BAU_MESSAGE;
2252 	for_each_possible_blade(uvhub) {
2253 		if (uv_blade_nr_possible_cpus(uvhub))
2254 			init_uvhub(uvhub, vector, uv_base_pnode);
2255 	}
2256 
2257 	for_each_possible_blade(uvhub) {
2258 		if (uv_blade_nr_possible_cpus(uvhub)) {
2259 			unsigned long val;
2260 			unsigned long mmr;
2261 			pnode = uv_blade_to_pnode(uvhub);
2262 			/* INIT the bau */
2263 			val = 1L << 63;
2264 			write_gmmr_activation(pnode, val);
2265 			mmr = 1; /* should be 1 to broadcast to both sockets */
2266 			if (!is_uv1_hub())
2267 				write_mmr_data_broadcast(pnode, mmr);
2268 		}
2269 	}
2270 
2271 	return 0;
2272 
2273 err_bau_disable:
2274 
2275 	for_each_possible_cpu(cur_cpu)
2276 		free_cpumask_var(per_cpu(uv_flush_tlb_mask, cur_cpu));
2277 
2278 	set_bau_off();
2279 	nobau_perm = 1;
2280 
2281 	return -EINVAL;
2282 }
2283 core_initcall(uv_bau_init);
2284 fs_initcall(uv_ptc_init);
2285