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Searched refs:dpll (Results 1 – 25 of 57) sorted by relevance

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/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
[all …]
/Linux-v4.19/drivers/gpu/drm/gma500/
Dpsb_intel_display.c116 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
165 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
166 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
172 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
173 dpll |= in psb_intel_crtc_mode_set()
178 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Dmdfld_intel_display.c275 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
282 REG_READ(map->dpll); in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
331 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
338 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
344 REG_READ(map->dpll); in mdfld_crtc_dpms()
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
349 REG_READ(map->dpll); in mdfld_crtc_dpms()
[all …]
Doaktrail_crtc.c250 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
252 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
261 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
263 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
322 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
324 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
326 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
[all …]
Dmdfld_device.c197 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
251 u32 dpll; in mdfld_restore_display_registers() local
258 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
284 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
289 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
291 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
295 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
296 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
297 PSB_WVDC32(dpll, map->dpll); in mdfld_restore_display_registers()
[all …]
Dcdv_intel_display.c591 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
673 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= 3; in cdv_intel_crtc_mode_set()
690 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
737 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
772 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
781 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
783 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c221 temp = REG_READ(map->dpll); in gma_crtc_dpms()
223 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
224 REG_READ(map->dpll); in gma_crtc_dpms()
227 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
228 REG_READ(map->dpll); in gma_crtc_dpms()
231 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
232 REG_READ(map->dpll); in gma_crtc_dpms()
307 temp = REG_READ(map->dpll); in gma_crtc_dpms()
309 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
310 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
Doaktrail_hdmi.c281 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
291 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
292 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
307 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
308 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c212 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
329 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
470 .dpll = MRST_DPLL_A,
494 .dpll = DPLL_B,
Dpsb_device.c269 .dpll = DPLL_A,
293 .dpll = DPLL_B,
/Linux-v4.19/arch/arm/mach-omap1/
Dsram.S39 strh r0, [r2] @ set dpll into bypass mode
44 strh r0, [r2] @ write new dpll value
52 lock: ldrh r4, [r2], #0 @ read back dpll value
55 tst r4, #1 << 0 @ dpll rate locked?
/Linux-v4.19/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c118 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
182 dpll->n = n; in rcar_du_dpll_divider()
183 dpll->m = m; in rcar_du_dpll_divider()
184 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
185 dpll->output = output; in rcar_du_dpll_divider()
197 dpll->output, dpll->fdpll, dpll->n, dpll->m, in rcar_du_dpll_divider()
226 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
247 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
248 extclk = dpll.output; in rcar_du_crtc_set_display_timing()
262 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
[all …]
/Linux-v4.19/drivers/ata/
Dpata_hpt3x2n.c316 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
323 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
332 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
334 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
336 flags |= dpll; in hpt3x2n_qc_issue()
339 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c979 int dpll, adjust; in hpt37x_init_one() local
982 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
984 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1012 if (dpll == 3) in hpt37x_init_one()
1018 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_display.c549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
590 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
611 const struct dpll *clock) in intel_PLL_is_valid()
684 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
685 struct dpll *best_clock) in i9xx_find_best_dpll()
688 struct dpll clock; in i9xx_find_best_dpll()
[all …]
Dintel_dpll_mgr.h141 uint32_t dpll; member
334 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
Dintel_dvo.c441 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init() local
478 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
479 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
486 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
/Linux-v4.19/drivers/video/fbdev/intelfb/
Dintelfbhw.c684 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
690 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
697 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
699 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
702 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
703 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1060 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1072 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
[all …]
/Linux-v4.19/arch/arm/boot/dts/
Domap54xx-clocks.dtsi107 compatible = "ti,omap4-dpll-m4xen-clock";
114 compatible = "ti,omap4-dpll-x2-clock";
180 compatible = "ti,omap4-dpll-core-clock";
187 compatible = "ti,omap4-dpll-x2-clock";
315 compatible = "ti,omap4-dpll-clock";
324 compatible = "ti,omap4-dpll-x2-clock";
360 compatible = "ti,omap5-mpu-dpll-clock";
524 compatible = "ti,omap4-dpll-clock";
531 compatible = "ti,omap4-dpll-x2-clock";
591 compatible = "ti,omap4-dpll-clock";
[all …]
Ddra7xx-clocks.dtsi201 compatible = "ti,omap4-dpll-m4xen-clock";
208 compatible = "ti,omap4-dpll-x2-clock";
264 compatible = "ti,omap4-dpll-core-clock";
271 compatible = "ti,omap4-dpll-x2-clock";
296 compatible = "ti,omap5-mpu-dpll-clock";
338 compatible = "ti,omap4-dpll-clock";
376 compatible = "ti,omap4-dpll-clock";
414 compatible = "ti,omap4-dpll-clock";
463 compatible = "ti,omap4-dpll-clock";
489 compatible = "ti,omap4-dpll-clock";
[all …]
Dam43xx-clocks.dtsi208 compatible = "ti,am3-dpll-core-clock";
215 compatible = "ti,am3-dpll-x2-clock";
254 compatible = "ti,am3-dpll-clock";
280 compatible = "ti,am3-dpll-clock";
298 compatible = "ti,am3-dpll-clock";
317 compatible = "ti,am3-dpll-j-type-clock";
561 compatible = "ti,am3-dpll-clock";
630 compatible = "ti,am3-dpll-x2-clock";
Dam33xx-clocks.dtsi168 compatible = "ti,am3-dpll-core-clock";
175 compatible = "ti,am3-dpll-x2-clock";
208 compatible = "ti,am3-dpll-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
Domap44xx-clocks.dtsi137 compatible = "ti,omap4-dpll-m4xen-clock";
144 compatible = "ti,omap4-dpll-x2-clock";
199 compatible = "ti,omap4-dpll-core-clock";
206 compatible = "ti,omap4-dpll-x2-clock";
349 compatible = "ti,omap4-dpll-clock";
358 compatible = "ti,omap4-dpll-x2-clock";
390 compatible = "ti,omap4-dpll-clock";
569 compatible = "ti,omap4-dpll-clock";
585 compatible = "ti,omap4-dpll-x2-clock";
670 compatible = "ti,omap4-dpll-j-type-clock";
/Linux-v4.19/drivers/clk/ti/
DMakefile5 clk-common = dpll.o composite.o divider.o gate.o \
/Linux-v4.19/arch/arm/mach-omap2/
Dsram243x.S268 str r0, [r4] @ set dpll ctrl val
281 beq pend @ jump over dpll relock
286 orr r8, r7, #0x3 @ val for lock dpll

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