Lines Matching refs:dpll
549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
590 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
611 const struct dpll *clock) in intel_PLL_is_valid()
684 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
685 struct dpll *best_clock) in i9xx_find_best_dpll()
688 struct dpll clock; in i9xx_find_best_dpll()
742 int target, int refclk, struct dpll *match_clock, in pnv_find_best_dpll()
743 struct dpll *best_clock) in pnv_find_best_dpll()
746 struct dpll clock; in pnv_find_best_dpll()
798 int target, int refclk, struct dpll *match_clock, in g4x_find_best_dpll()
799 struct dpll *best_clock) in g4x_find_best_dpll()
802 struct dpll clock; in g4x_find_best_dpll()
849 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
850 const struct dpll *best_clock, in vlv_PLL_is_optimal()
892 int target, int refclk, struct dpll *match_clock, in vlv_find_best_dpll()
893 struct dpll *best_clock) in vlv_find_best_dpll()
897 struct dpll clock; in vlv_find_best_dpll()
952 int target, int refclk, struct dpll *match_clock, in chv_find_best_dpll()
953 struct dpll *best_clock) in chv_find_best_dpll()
958 struct dpll clock; in chv_find_best_dpll()
1008 struct dpll *best_clock) in bxt_find_best_dpll()
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1512 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1529 dpll |= DPLL_DVO_2X_MODE; in i9xx_enable_pll()
1541 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1556 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1561 I915_WRITE(reg, dpll); in i9xx_enable_pll()
6730 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
6732 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
6735 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
6737 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
6742 struct dpll *reduced_clock) in i9xx_update_pll_dividers()
6748 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6752 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6870 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
6873 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
6877 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
6887 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
6890 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
6894 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
6912 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
6916 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
6921 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
6922 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
6923 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
6924 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
6925 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
7013 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7016 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
7019 bestn = pipe_config->dpll.n; in chv_prepare_pll()
7020 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
7021 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
7022 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
7023 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
7024 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
7025 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7115 const struct dpll *dpll) in vlv_force_pll_on() argument
7126 pipe_config->dpll = *dpll; in vlv_force_pll_on()
7161 struct dpll *reduced_clock) in i9xx_compute_dpll()
7164 u32 dpll; in i9xx_compute_dpll() local
7165 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
7169 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
7172 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
7174 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
7178 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
7184 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
7187 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
7191 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
7193 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
7195 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
7199 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
7202 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
7205 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
7208 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
7212 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
7215 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
7218 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
7220 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
7222 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
7223 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
7234 struct dpll *reduced_clock) in i8xx_compute_dpll()
7238 u32 dpll; in i8xx_compute_dpll() local
7239 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
7243 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
7246 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
7249 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
7251 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
7253 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
7258 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
7262 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
7264 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
7266 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
7267 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
7499 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
7542 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
7576 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
7610 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
7631 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
7652 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
7695 struct dpll clock; in vlv_crtc_clock_get()
7700 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
7799 struct dpll clock; in chv_crtc_clock_get()
7804 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
7898 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7906 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
7912 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
8481 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) in ironlake_needs_fb_cb_tune() argument
8483 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ironlake_needs_fb_cb_tune()
8488 struct dpll *reduced_clock) in ironlake_compute_dpll()
8493 u32 dpll, fp, fp2; in ironlake_compute_dpll() local
8506 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_compute_dpll()
8508 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
8520 dpll = 0; in ironlake_compute_dpll()
8523 dpll |= DPLLB_MODE_LVDS; in ironlake_compute_dpll()
8525 dpll |= DPLLB_MODE_DAC_SERIAL; in ironlake_compute_dpll()
8527 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
8532 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
8535 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
8553 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
8556 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8558 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8560 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
8562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ironlake_compute_dpll()
8565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ironlake_compute_dpll()
8568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ironlake_compute_dpll()
8571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ironlake_compute_dpll()
8577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ironlake_compute_dpll()
8579 dpll |= PLL_REF_INPUT_DREFCLK; in ironlake_compute_dpll()
8581 dpll |= DPLL_VCO_ENABLE; in ironlake_compute_dpll()
8583 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_compute_dpll()
8627 refclk, NULL, &crtc_state->dpll)) { in ironlake_crtc_compute_clock()
8949 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
10278 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
10280 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
10297 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
10299 struct dpll clock; in i9xx_crtc_clock_get()
10303 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
10319 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
10322 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
10325 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
10327 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
10331 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
10336 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
10349 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
10357 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
10360 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
10363 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
11547 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
15280 struct dpll clock = { in i830_enable_pipe()
15287 u32 dpll, fp; in i830_enable_pipe() local
15296 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | in i830_enable_pipe()
15319 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
15320 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()
15331 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()
15335 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()