1/* 2 * Device Tree Source for OMAP4 clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&cm1_clocks { 11 extalt_clkin_ck: extalt_clkin_ck { 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <59000000>; 15 }; 16 17 pad_clks_src_ck: pad_clks_src_ck { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <12000000>; 21 }; 22 23 pad_clks_ck: pad_clks_ck@108 { 24 #clock-cells = <0>; 25 compatible = "ti,gate-clock"; 26 clocks = <&pad_clks_src_ck>; 27 ti,bit-shift = <8>; 28 reg = <0x0108>; 29 }; 30 31 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <12000000>; 35 }; 36 37 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 38 #clock-cells = <0>; 39 compatible = "fixed-clock"; 40 clock-frequency = <32768>; 41 }; 42 43 slimbus_src_clk: slimbus_src_clk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <12000000>; 47 }; 48 49 slimbus_clk: slimbus_clk@108 { 50 #clock-cells = <0>; 51 compatible = "ti,gate-clock"; 52 clocks = <&slimbus_src_clk>; 53 ti,bit-shift = <10>; 54 reg = <0x0108>; 55 }; 56 57 sys_32k_ck: sys_32k_ck { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 virt_12000000_ck: virt_12000000_ck { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <12000000>; 67 }; 68 69 virt_13000000_ck: virt_13000000_ck { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <13000000>; 73 }; 74 75 virt_16800000_ck: virt_16800000_ck { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <16800000>; 79 }; 80 81 virt_19200000_ck: virt_19200000_ck { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <19200000>; 85 }; 86 87 virt_26000000_ck: virt_26000000_ck { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <26000000>; 91 }; 92 93 virt_27000000_ck: virt_27000000_ck { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <27000000>; 97 }; 98 99 virt_38400000_ck: virt_38400000_ck { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <38400000>; 103 }; 104 105 tie_low_clock_ck: tie_low_clock_ck { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <0>; 109 }; 110 111 utmi_phy_clkout_ck: utmi_phy_clkout_ck { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <60000000>; 115 }; 116 117 xclk60mhsp1_ck: xclk60mhsp1_ck { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 clock-frequency = <60000000>; 121 }; 122 123 xclk60mhsp2_ck: xclk60mhsp2_ck { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <60000000>; 127 }; 128 129 xclk60motg_ck: xclk60motg_ck { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-frequency = <60000000>; 133 }; 134 135 dpll_abe_ck: dpll_abe_ck@1e0 { 136 #clock-cells = <0>; 137 compatible = "ti,omap4-dpll-m4xen-clock"; 138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; 139 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 140 }; 141 142 dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { 143 #clock-cells = <0>; 144 compatible = "ti,omap4-dpll-x2-clock"; 145 clocks = <&dpll_abe_ck>; 146 reg = <0x01f0>; 147 }; 148 149 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { 150 #clock-cells = <0>; 151 compatible = "ti,divider-clock"; 152 clocks = <&dpll_abe_x2_ck>; 153 ti,max-div = <31>; 154 ti,autoidle-shift = <8>; 155 reg = <0x01f0>; 156 ti,index-starts-at-one; 157 ti,invert-autoidle-bit; 158 }; 159 160 abe_24m_fclk: abe_24m_fclk { 161 #clock-cells = <0>; 162 compatible = "fixed-factor-clock"; 163 clocks = <&dpll_abe_m2x2_ck>; 164 clock-mult = <1>; 165 clock-div = <8>; 166 }; 167 168 abe_clk: abe_clk@108 { 169 #clock-cells = <0>; 170 compatible = "ti,divider-clock"; 171 clocks = <&dpll_abe_m2x2_ck>; 172 ti,max-div = <4>; 173 reg = <0x0108>; 174 ti,index-power-of-two; 175 }; 176 177 178 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { 179 #clock-cells = <0>; 180 compatible = "ti,divider-clock"; 181 clocks = <&dpll_abe_x2_ck>; 182 ti,max-div = <31>; 183 ti,autoidle-shift = <8>; 184 reg = <0x01f4>; 185 ti,index-starts-at-one; 186 ti,invert-autoidle-bit; 187 }; 188 189 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { 190 #clock-cells = <0>; 191 compatible = "ti,mux-clock"; 192 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; 193 ti,bit-shift = <23>; 194 reg = <0x012c>; 195 }; 196 197 dpll_core_ck: dpll_core_ck@120 { 198 #clock-cells = <0>; 199 compatible = "ti,omap4-dpll-core-clock"; 200 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; 201 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 202 }; 203 204 dpll_core_x2_ck: dpll_core_x2_ck { 205 #clock-cells = <0>; 206 compatible = "ti,omap4-dpll-x2-clock"; 207 clocks = <&dpll_core_ck>; 208 }; 209 210 dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { 211 #clock-cells = <0>; 212 compatible = "ti,divider-clock"; 213 clocks = <&dpll_core_x2_ck>; 214 ti,max-div = <31>; 215 ti,autoidle-shift = <8>; 216 reg = <0x0140>; 217 ti,index-starts-at-one; 218 ti,invert-autoidle-bit; 219 }; 220 221 dpll_core_m2_ck: dpll_core_m2_ck@130 { 222 #clock-cells = <0>; 223 compatible = "ti,divider-clock"; 224 clocks = <&dpll_core_ck>; 225 ti,max-div = <31>; 226 ti,autoidle-shift = <8>; 227 reg = <0x0130>; 228 ti,index-starts-at-one; 229 ti,invert-autoidle-bit; 230 }; 231 232 ddrphy_ck: ddrphy_ck { 233 #clock-cells = <0>; 234 compatible = "fixed-factor-clock"; 235 clocks = <&dpll_core_m2_ck>; 236 clock-mult = <1>; 237 clock-div = <2>; 238 }; 239 240 dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { 241 #clock-cells = <0>; 242 compatible = "ti,divider-clock"; 243 clocks = <&dpll_core_x2_ck>; 244 ti,max-div = <31>; 245 ti,autoidle-shift = <8>; 246 reg = <0x013c>; 247 ti,index-starts-at-one; 248 ti,invert-autoidle-bit; 249 }; 250 251 div_core_ck: div_core_ck@100 { 252 #clock-cells = <0>; 253 compatible = "ti,divider-clock"; 254 clocks = <&dpll_core_m5x2_ck>; 255 reg = <0x0100>; 256 ti,max-div = <2>; 257 }; 258 259 div_iva_hs_clk: div_iva_hs_clk@1dc { 260 #clock-cells = <0>; 261 compatible = "ti,divider-clock"; 262 clocks = <&dpll_core_m5x2_ck>; 263 ti,max-div = <4>; 264 reg = <0x01dc>; 265 ti,index-power-of-two; 266 }; 267 268 div_mpu_hs_clk: div_mpu_hs_clk@19c { 269 #clock-cells = <0>; 270 compatible = "ti,divider-clock"; 271 clocks = <&dpll_core_m5x2_ck>; 272 ti,max-div = <4>; 273 reg = <0x019c>; 274 ti,index-power-of-two; 275 }; 276 277 dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { 278 #clock-cells = <0>; 279 compatible = "ti,divider-clock"; 280 clocks = <&dpll_core_x2_ck>; 281 ti,max-div = <31>; 282 ti,autoidle-shift = <8>; 283 reg = <0x0138>; 284 ti,index-starts-at-one; 285 ti,invert-autoidle-bit; 286 }; 287 288 dll_clk_div_ck: dll_clk_div_ck { 289 #clock-cells = <0>; 290 compatible = "fixed-factor-clock"; 291 clocks = <&dpll_core_m4x2_ck>; 292 clock-mult = <1>; 293 clock-div = <2>; 294 }; 295 296 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { 297 #clock-cells = <0>; 298 compatible = "ti,divider-clock"; 299 clocks = <&dpll_abe_ck>; 300 ti,max-div = <31>; 301 reg = <0x01f0>; 302 ti,index-starts-at-one; 303 }; 304 305 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { 306 #clock-cells = <0>; 307 compatible = "ti,composite-no-wait-gate-clock"; 308 clocks = <&dpll_core_x2_ck>; 309 ti,bit-shift = <8>; 310 reg = <0x0134>; 311 }; 312 313 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { 314 #clock-cells = <0>; 315 compatible = "ti,composite-divider-clock"; 316 clocks = <&dpll_core_x2_ck>; 317 ti,max-div = <31>; 318 reg = <0x0134>; 319 ti,index-starts-at-one; 320 }; 321 322 dpll_core_m3x2_ck: dpll_core_m3x2_ck { 323 #clock-cells = <0>; 324 compatible = "ti,composite-clock"; 325 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; 326 }; 327 328 dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { 329 #clock-cells = <0>; 330 compatible = "ti,divider-clock"; 331 clocks = <&dpll_core_x2_ck>; 332 ti,max-div = <31>; 333 ti,autoidle-shift = <8>; 334 reg = <0x0144>; 335 ti,index-starts-at-one; 336 ti,invert-autoidle-bit; 337 }; 338 339 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { 340 #clock-cells = <0>; 341 compatible = "ti,mux-clock"; 342 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; 343 ti,bit-shift = <23>; 344 reg = <0x01ac>; 345 }; 346 347 dpll_iva_ck: dpll_iva_ck@1a0 { 348 #clock-cells = <0>; 349 compatible = "ti,omap4-dpll-clock"; 350 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; 351 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 352 assigned-clocks = <&dpll_iva_ck>; 353 assigned-clock-rates = <931200000>; 354 }; 355 356 dpll_iva_x2_ck: dpll_iva_x2_ck { 357 #clock-cells = <0>; 358 compatible = "ti,omap4-dpll-x2-clock"; 359 clocks = <&dpll_iva_ck>; 360 }; 361 362 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { 363 #clock-cells = <0>; 364 compatible = "ti,divider-clock"; 365 clocks = <&dpll_iva_x2_ck>; 366 ti,max-div = <31>; 367 ti,autoidle-shift = <8>; 368 reg = <0x01b8>; 369 ti,index-starts-at-one; 370 ti,invert-autoidle-bit; 371 assigned-clocks = <&dpll_iva_m4x2_ck>; 372 assigned-clock-rates = <465600000>; 373 }; 374 375 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { 376 #clock-cells = <0>; 377 compatible = "ti,divider-clock"; 378 clocks = <&dpll_iva_x2_ck>; 379 ti,max-div = <31>; 380 ti,autoidle-shift = <8>; 381 reg = <0x01bc>; 382 ti,index-starts-at-one; 383 ti,invert-autoidle-bit; 384 assigned-clocks = <&dpll_iva_m5x2_ck>; 385 assigned-clock-rates = <266100000>; 386 }; 387 388 dpll_mpu_ck: dpll_mpu_ck@160 { 389 #clock-cells = <0>; 390 compatible = "ti,omap4-dpll-clock"; 391 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; 392 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 393 }; 394 395 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { 396 #clock-cells = <0>; 397 compatible = "ti,divider-clock"; 398 clocks = <&dpll_mpu_ck>; 399 ti,max-div = <31>; 400 ti,autoidle-shift = <8>; 401 reg = <0x0170>; 402 ti,index-starts-at-one; 403 ti,invert-autoidle-bit; 404 }; 405 406 per_hs_clk_div_ck: per_hs_clk_div_ck { 407 #clock-cells = <0>; 408 compatible = "fixed-factor-clock"; 409 clocks = <&dpll_abe_m3x2_ck>; 410 clock-mult = <1>; 411 clock-div = <2>; 412 }; 413 414 usb_hs_clk_div_ck: usb_hs_clk_div_ck { 415 #clock-cells = <0>; 416 compatible = "fixed-factor-clock"; 417 clocks = <&dpll_abe_m3x2_ck>; 418 clock-mult = <1>; 419 clock-div = <3>; 420 }; 421 422 l3_div_ck: l3_div_ck@100 { 423 #clock-cells = <0>; 424 compatible = "ti,divider-clock"; 425 clocks = <&div_core_ck>; 426 ti,bit-shift = <4>; 427 ti,max-div = <2>; 428 reg = <0x0100>; 429 }; 430 431 l4_div_ck: l4_div_ck@100 { 432 #clock-cells = <0>; 433 compatible = "ti,divider-clock"; 434 clocks = <&l3_div_ck>; 435 ti,bit-shift = <8>; 436 ti,max-div = <2>; 437 reg = <0x0100>; 438 }; 439 440 lp_clk_div_ck: lp_clk_div_ck { 441 #clock-cells = <0>; 442 compatible = "fixed-factor-clock"; 443 clocks = <&dpll_abe_m2x2_ck>; 444 clock-mult = <1>; 445 clock-div = <16>; 446 }; 447 448 mpu_periphclk: mpu_periphclk { 449 #clock-cells = <0>; 450 compatible = "fixed-factor-clock"; 451 clocks = <&dpll_mpu_ck>; 452 clock-mult = <1>; 453 clock-div = <2>; 454 }; 455 456 ocp_abe_iclk: ocp_abe_iclk@528 { 457 #clock-cells = <0>; 458 compatible = "ti,divider-clock"; 459 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; 460 ti,bit-shift = <24>; 461 reg = <0x0528>; 462 ti,dividers = <2>, <1>; 463 }; 464 465 per_abe_24m_fclk: per_abe_24m_fclk { 466 #clock-cells = <0>; 467 compatible = "fixed-factor-clock"; 468 clocks = <&dpll_abe_m2_ck>; 469 clock-mult = <1>; 470 clock-div = <4>; 471 }; 472 473 dummy_ck: dummy_ck { 474 #clock-cells = <0>; 475 compatible = "fixed-clock"; 476 clock-frequency = <0>; 477 }; 478}; 479 480&prm_clocks { 481 sys_clkin_ck: sys_clkin_ck@110 { 482 #clock-cells = <0>; 483 compatible = "ti,mux-clock"; 484 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 485 reg = <0x0110>; 486 ti,index-starts-at-one; 487 }; 488 489 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { 490 #clock-cells = <0>; 491 compatible = "ti,mux-clock"; 492 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 493 ti,bit-shift = <24>; 494 reg = <0x0108>; 495 }; 496 497 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { 498 #clock-cells = <0>; 499 compatible = "ti,mux-clock"; 500 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 501 reg = <0x010c>; 502 }; 503 504 dbgclk_mux_ck: dbgclk_mux_ck { 505 #clock-cells = <0>; 506 compatible = "fixed-factor-clock"; 507 clocks = <&sys_clkin_ck>; 508 clock-mult = <1>; 509 clock-div = <1>; 510 }; 511 512 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { 513 #clock-cells = <0>; 514 compatible = "ti,mux-clock"; 515 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; 516 reg = <0x0108>; 517 }; 518 519 syc_clk_div_ck: syc_clk_div_ck@100 { 520 #clock-cells = <0>; 521 compatible = "ti,divider-clock"; 522 clocks = <&sys_clkin_ck>; 523 reg = <0x0100>; 524 ti,max-div = <2>; 525 }; 526 527 usim_ck: usim_ck@1858 { 528 #clock-cells = <0>; 529 compatible = "ti,divider-clock"; 530 clocks = <&dpll_per_m4x2_ck>; 531 ti,bit-shift = <24>; 532 reg = <0x1858>; 533 ti,dividers = <14>, <18>; 534 }; 535 536 usim_fclk: usim_fclk@1858 { 537 #clock-cells = <0>; 538 compatible = "ti,gate-clock"; 539 clocks = <&usim_ck>; 540 ti,bit-shift = <8>; 541 reg = <0x1858>; 542 }; 543 544 trace_clk_div_ck: trace_clk_div_ck { 545 #clock-cells = <0>; 546 compatible = "ti,clkdm-gate-clock"; 547 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; 548 }; 549}; 550 551&prm_clockdomains { 552 emu_sys_clkdm: emu_sys_clkdm { 553 compatible = "ti,clockdomain"; 554 clocks = <&trace_clk_div_ck>; 555 }; 556}; 557 558&cm2_clocks { 559 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { 560 #clock-cells = <0>; 561 compatible = "ti,mux-clock"; 562 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; 563 ti,bit-shift = <23>; 564 reg = <0x014c>; 565 }; 566 567 dpll_per_ck: dpll_per_ck@140 { 568 #clock-cells = <0>; 569 compatible = "ti,omap4-dpll-clock"; 570 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; 571 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 572 }; 573 574 dpll_per_m2_ck: dpll_per_m2_ck@150 { 575 #clock-cells = <0>; 576 compatible = "ti,divider-clock"; 577 clocks = <&dpll_per_ck>; 578 ti,max-div = <31>; 579 reg = <0x0150>; 580 ti,index-starts-at-one; 581 }; 582 583 dpll_per_x2_ck: dpll_per_x2_ck@150 { 584 #clock-cells = <0>; 585 compatible = "ti,omap4-dpll-x2-clock"; 586 clocks = <&dpll_per_ck>; 587 reg = <0x0150>; 588 }; 589 590 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { 591 #clock-cells = <0>; 592 compatible = "ti,divider-clock"; 593 clocks = <&dpll_per_x2_ck>; 594 ti,max-div = <31>; 595 ti,autoidle-shift = <8>; 596 reg = <0x0150>; 597 ti,index-starts-at-one; 598 ti,invert-autoidle-bit; 599 }; 600 601 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { 602 #clock-cells = <0>; 603 compatible = "ti,composite-no-wait-gate-clock"; 604 clocks = <&dpll_per_x2_ck>; 605 ti,bit-shift = <8>; 606 reg = <0x0154>; 607 }; 608 609 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { 610 #clock-cells = <0>; 611 compatible = "ti,composite-divider-clock"; 612 clocks = <&dpll_per_x2_ck>; 613 ti,max-div = <31>; 614 reg = <0x0154>; 615 ti,index-starts-at-one; 616 }; 617 618 dpll_per_m3x2_ck: dpll_per_m3x2_ck { 619 #clock-cells = <0>; 620 compatible = "ti,composite-clock"; 621 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; 622 }; 623 624 dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { 625 #clock-cells = <0>; 626 compatible = "ti,divider-clock"; 627 clocks = <&dpll_per_x2_ck>; 628 ti,max-div = <31>; 629 ti,autoidle-shift = <8>; 630 reg = <0x0158>; 631 ti,index-starts-at-one; 632 ti,invert-autoidle-bit; 633 }; 634 635 dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { 636 #clock-cells = <0>; 637 compatible = "ti,divider-clock"; 638 clocks = <&dpll_per_x2_ck>; 639 ti,max-div = <31>; 640 ti,autoidle-shift = <8>; 641 reg = <0x015c>; 642 ti,index-starts-at-one; 643 ti,invert-autoidle-bit; 644 }; 645 646 dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { 647 #clock-cells = <0>; 648 compatible = "ti,divider-clock"; 649 clocks = <&dpll_per_x2_ck>; 650 ti,max-div = <31>; 651 ti,autoidle-shift = <8>; 652 reg = <0x0160>; 653 ti,index-starts-at-one; 654 ti,invert-autoidle-bit; 655 }; 656 657 dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { 658 #clock-cells = <0>; 659 compatible = "ti,divider-clock"; 660 clocks = <&dpll_per_x2_ck>; 661 ti,max-div = <31>; 662 ti,autoidle-shift = <8>; 663 reg = <0x0164>; 664 ti,index-starts-at-one; 665 ti,invert-autoidle-bit; 666 }; 667 668 dpll_usb_ck: dpll_usb_ck@180 { 669 #clock-cells = <0>; 670 compatible = "ti,omap4-dpll-j-type-clock"; 671 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; 672 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 673 }; 674 675 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { 676 #clock-cells = <0>; 677 compatible = "ti,fixed-factor-clock"; 678 clocks = <&dpll_usb_ck>; 679 ti,clock-div = <1>; 680 ti,autoidle-shift = <8>; 681 reg = <0x01b4>; 682 ti,clock-mult = <1>; 683 ti,invert-autoidle-bit; 684 }; 685 686 dpll_usb_m2_ck: dpll_usb_m2_ck@190 { 687 #clock-cells = <0>; 688 compatible = "ti,divider-clock"; 689 clocks = <&dpll_usb_ck>; 690 ti,max-div = <127>; 691 ti,autoidle-shift = <8>; 692 reg = <0x0190>; 693 ti,index-starts-at-one; 694 ti,invert-autoidle-bit; 695 }; 696 697 ducati_clk_mux_ck: ducati_clk_mux_ck@100 { 698 #clock-cells = <0>; 699 compatible = "ti,mux-clock"; 700 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; 701 reg = <0x0100>; 702 }; 703 704 func_12m_fclk: func_12m_fclk { 705 #clock-cells = <0>; 706 compatible = "fixed-factor-clock"; 707 clocks = <&dpll_per_m2x2_ck>; 708 clock-mult = <1>; 709 clock-div = <16>; 710 }; 711 712 func_24m_clk: func_24m_clk { 713 #clock-cells = <0>; 714 compatible = "fixed-factor-clock"; 715 clocks = <&dpll_per_m2_ck>; 716 clock-mult = <1>; 717 clock-div = <4>; 718 }; 719 720 func_24mc_fclk: func_24mc_fclk { 721 #clock-cells = <0>; 722 compatible = "fixed-factor-clock"; 723 clocks = <&dpll_per_m2x2_ck>; 724 clock-mult = <1>; 725 clock-div = <8>; 726 }; 727 728 func_48m_fclk: func_48m_fclk@108 { 729 #clock-cells = <0>; 730 compatible = "ti,divider-clock"; 731 clocks = <&dpll_per_m2x2_ck>; 732 reg = <0x0108>; 733 ti,dividers = <4>, <8>; 734 }; 735 736 func_48mc_fclk: func_48mc_fclk { 737 #clock-cells = <0>; 738 compatible = "fixed-factor-clock"; 739 clocks = <&dpll_per_m2x2_ck>; 740 clock-mult = <1>; 741 clock-div = <4>; 742 }; 743 744 func_64m_fclk: func_64m_fclk@108 { 745 #clock-cells = <0>; 746 compatible = "ti,divider-clock"; 747 clocks = <&dpll_per_m4x2_ck>; 748 reg = <0x0108>; 749 ti,dividers = <2>, <4>; 750 }; 751 752 func_96m_fclk: func_96m_fclk@108 { 753 #clock-cells = <0>; 754 compatible = "ti,divider-clock"; 755 clocks = <&dpll_per_m2x2_ck>; 756 reg = <0x0108>; 757 ti,dividers = <2>, <4>; 758 }; 759 760 init_60m_fclk: init_60m_fclk@104 { 761 #clock-cells = <0>; 762 compatible = "ti,divider-clock"; 763 clocks = <&dpll_usb_m2_ck>; 764 reg = <0x0104>; 765 ti,dividers = <1>, <8>; 766 }; 767 768 per_abe_nc_fclk: per_abe_nc_fclk@108 { 769 #clock-cells = <0>; 770 compatible = "ti,divider-clock"; 771 clocks = <&dpll_abe_m2_ck>; 772 reg = <0x0108>; 773 ti,max-div = <2>; 774 }; 775 776 sha2md5_fck: sha2md5_fck@15c8 { 777 #clock-cells = <0>; 778 compatible = "ti,gate-clock"; 779 clocks = <&l3_div_ck>; 780 ti,bit-shift = <1>; 781 reg = <0x15c8>; 782 }; 783 784 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { 785 #clock-cells = <0>; 786 compatible = "ti,gate-clock"; 787 clocks = <&sys_32k_ck>; 788 ti,bit-shift = <8>; 789 reg = <0x0640>; 790 }; 791}; 792 793&cm2_clockdomains { 794 l3_init_clkdm: l3_init_clkdm { 795 compatible = "ti,clockdomain"; 796 clocks = <&dpll_usb_ck>; 797 }; 798}; 799 800&scrm_clocks { 801 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { 802 #clock-cells = <0>; 803 compatible = "ti,composite-no-wait-gate-clock"; 804 clocks = <&dpll_core_m3x2_ck>; 805 ti,bit-shift = <8>; 806 reg = <0x0310>; 807 }; 808 809 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { 810 #clock-cells = <0>; 811 compatible = "ti,composite-mux-clock"; 812 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 813 ti,bit-shift = <1>; 814 reg = <0x0310>; 815 }; 816 817 auxclk0_src_ck: auxclk0_src_ck { 818 #clock-cells = <0>; 819 compatible = "ti,composite-clock"; 820 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 821 }; 822 823 auxclk0_ck: auxclk0_ck@310 { 824 #clock-cells = <0>; 825 compatible = "ti,divider-clock"; 826 clocks = <&auxclk0_src_ck>; 827 ti,bit-shift = <16>; 828 ti,max-div = <16>; 829 reg = <0x0310>; 830 }; 831 832 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { 833 #clock-cells = <0>; 834 compatible = "ti,composite-no-wait-gate-clock"; 835 clocks = <&dpll_core_m3x2_ck>; 836 ti,bit-shift = <8>; 837 reg = <0x0314>; 838 }; 839 840 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { 841 #clock-cells = <0>; 842 compatible = "ti,composite-mux-clock"; 843 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 844 ti,bit-shift = <1>; 845 reg = <0x0314>; 846 }; 847 848 auxclk1_src_ck: auxclk1_src_ck { 849 #clock-cells = <0>; 850 compatible = "ti,composite-clock"; 851 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 852 }; 853 854 auxclk1_ck: auxclk1_ck@314 { 855 #clock-cells = <0>; 856 compatible = "ti,divider-clock"; 857 clocks = <&auxclk1_src_ck>; 858 ti,bit-shift = <16>; 859 ti,max-div = <16>; 860 reg = <0x0314>; 861 }; 862 863 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { 864 #clock-cells = <0>; 865 compatible = "ti,composite-no-wait-gate-clock"; 866 clocks = <&dpll_core_m3x2_ck>; 867 ti,bit-shift = <8>; 868 reg = <0x0318>; 869 }; 870 871 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { 872 #clock-cells = <0>; 873 compatible = "ti,composite-mux-clock"; 874 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 875 ti,bit-shift = <1>; 876 reg = <0x0318>; 877 }; 878 879 auxclk2_src_ck: auxclk2_src_ck { 880 #clock-cells = <0>; 881 compatible = "ti,composite-clock"; 882 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 883 }; 884 885 auxclk2_ck: auxclk2_ck@318 { 886 #clock-cells = <0>; 887 compatible = "ti,divider-clock"; 888 clocks = <&auxclk2_src_ck>; 889 ti,bit-shift = <16>; 890 ti,max-div = <16>; 891 reg = <0x0318>; 892 }; 893 894 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { 895 #clock-cells = <0>; 896 compatible = "ti,composite-no-wait-gate-clock"; 897 clocks = <&dpll_core_m3x2_ck>; 898 ti,bit-shift = <8>; 899 reg = <0x031c>; 900 }; 901 902 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { 903 #clock-cells = <0>; 904 compatible = "ti,composite-mux-clock"; 905 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 906 ti,bit-shift = <1>; 907 reg = <0x031c>; 908 }; 909 910 auxclk3_src_ck: auxclk3_src_ck { 911 #clock-cells = <0>; 912 compatible = "ti,composite-clock"; 913 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 914 }; 915 916 auxclk3_ck: auxclk3_ck@31c { 917 #clock-cells = <0>; 918 compatible = "ti,divider-clock"; 919 clocks = <&auxclk3_src_ck>; 920 ti,bit-shift = <16>; 921 ti,max-div = <16>; 922 reg = <0x031c>; 923 }; 924 925 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { 926 #clock-cells = <0>; 927 compatible = "ti,composite-no-wait-gate-clock"; 928 clocks = <&dpll_core_m3x2_ck>; 929 ti,bit-shift = <8>; 930 reg = <0x0320>; 931 }; 932 933 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { 934 #clock-cells = <0>; 935 compatible = "ti,composite-mux-clock"; 936 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 937 ti,bit-shift = <1>; 938 reg = <0x0320>; 939 }; 940 941 auxclk4_src_ck: auxclk4_src_ck { 942 #clock-cells = <0>; 943 compatible = "ti,composite-clock"; 944 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 945 }; 946 947 auxclk4_ck: auxclk4_ck@320 { 948 #clock-cells = <0>; 949 compatible = "ti,divider-clock"; 950 clocks = <&auxclk4_src_ck>; 951 ti,bit-shift = <16>; 952 ti,max-div = <16>; 953 reg = <0x0320>; 954 }; 955 956 auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { 957 #clock-cells = <0>; 958 compatible = "ti,composite-no-wait-gate-clock"; 959 clocks = <&dpll_core_m3x2_ck>; 960 ti,bit-shift = <8>; 961 reg = <0x0324>; 962 }; 963 964 auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { 965 #clock-cells = <0>; 966 compatible = "ti,composite-mux-clock"; 967 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 968 ti,bit-shift = <1>; 969 reg = <0x0324>; 970 }; 971 972 auxclk5_src_ck: auxclk5_src_ck { 973 #clock-cells = <0>; 974 compatible = "ti,composite-clock"; 975 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; 976 }; 977 978 auxclk5_ck: auxclk5_ck@324 { 979 #clock-cells = <0>; 980 compatible = "ti,divider-clock"; 981 clocks = <&auxclk5_src_ck>; 982 ti,bit-shift = <16>; 983 ti,max-div = <16>; 984 reg = <0x0324>; 985 }; 986 987 auxclkreq0_ck: auxclkreq0_ck@210 { 988 #clock-cells = <0>; 989 compatible = "ti,mux-clock"; 990 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 991 ti,bit-shift = <2>; 992 reg = <0x0210>; 993 }; 994 995 auxclkreq1_ck: auxclkreq1_ck@214 { 996 #clock-cells = <0>; 997 compatible = "ti,mux-clock"; 998 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 999 ti,bit-shift = <2>; 1000 reg = <0x0214>; 1001 }; 1002 1003 auxclkreq2_ck: auxclkreq2_ck@218 { 1004 #clock-cells = <0>; 1005 compatible = "ti,mux-clock"; 1006 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1007 ti,bit-shift = <2>; 1008 reg = <0x0218>; 1009 }; 1010 1011 auxclkreq3_ck: auxclkreq3_ck@21c { 1012 #clock-cells = <0>; 1013 compatible = "ti,mux-clock"; 1014 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1015 ti,bit-shift = <2>; 1016 reg = <0x021c>; 1017 }; 1018 1019 auxclkreq4_ck: auxclkreq4_ck@220 { 1020 #clock-cells = <0>; 1021 compatible = "ti,mux-clock"; 1022 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1023 ti,bit-shift = <2>; 1024 reg = <0x0220>; 1025 }; 1026 1027 auxclkreq5_ck: auxclkreq5_ck@224 { 1028 #clock-cells = <0>; 1029 compatible = "ti,mux-clock"; 1030 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1031 ti,bit-shift = <2>; 1032 reg = <0x0224>; 1033 }; 1034}; 1035 1036&cm1 { 1037 mpuss_cm: mpuss_cm@300 { 1038 compatible = "ti,omap4-cm"; 1039 reg = <0x300 0x100>; 1040 #address-cells = <1>; 1041 #size-cells = <1>; 1042 ranges = <0 0x300 0x100>; 1043 1044 mpuss_clkctrl: clk@20 { 1045 compatible = "ti,clkctrl"; 1046 reg = <0x20 0x4>; 1047 #clock-cells = <2>; 1048 }; 1049 }; 1050 1051 tesla_cm: tesla_cm@400 { 1052 compatible = "ti,omap4-cm"; 1053 reg = <0x400 0x100>; 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 ranges = <0 0x400 0x100>; 1057 1058 tesla_clkctrl: clk@20 { 1059 compatible = "ti,clkctrl"; 1060 reg = <0x20 0x4>; 1061 #clock-cells = <2>; 1062 }; 1063 }; 1064 1065 abe_cm: abe_cm@500 { 1066 compatible = "ti,omap4-cm"; 1067 reg = <0x500 0x100>; 1068 #address-cells = <1>; 1069 #size-cells = <1>; 1070 ranges = <0 0x500 0x100>; 1071 1072 abe_clkctrl: clk@20 { 1073 compatible = "ti,clkctrl"; 1074 reg = <0x20 0x6c>; 1075 #clock-cells = <2>; 1076 }; 1077 }; 1078 1079}; 1080 1081&cm2 { 1082 l4_ao_cm: l4_ao_cm@600 { 1083 compatible = "ti,omap4-cm"; 1084 reg = <0x600 0x100>; 1085 #address-cells = <1>; 1086 #size-cells = <1>; 1087 ranges = <0 0x600 0x100>; 1088 1089 l4_ao_clkctrl: clk@20 { 1090 compatible = "ti,clkctrl"; 1091 reg = <0x20 0x1c>; 1092 #clock-cells = <2>; 1093 }; 1094 }; 1095 1096 l3_1_cm: l3_1_cm@700 { 1097 compatible = "ti,omap4-cm"; 1098 reg = <0x700 0x100>; 1099 #address-cells = <1>; 1100 #size-cells = <1>; 1101 ranges = <0 0x700 0x100>; 1102 1103 l3_1_clkctrl: clk@20 { 1104 compatible = "ti,clkctrl"; 1105 reg = <0x20 0x4>; 1106 #clock-cells = <2>; 1107 }; 1108 }; 1109 1110 l3_2_cm: l3_2_cm@800 { 1111 compatible = "ti,omap4-cm"; 1112 reg = <0x800 0x100>; 1113 #address-cells = <1>; 1114 #size-cells = <1>; 1115 ranges = <0 0x800 0x100>; 1116 1117 l3_2_clkctrl: clk@20 { 1118 compatible = "ti,clkctrl"; 1119 reg = <0x20 0x14>; 1120 #clock-cells = <2>; 1121 }; 1122 }; 1123 1124 ducati_cm: ducati_cm@900 { 1125 compatible = "ti,omap4-cm"; 1126 reg = <0x900 0x100>; 1127 #address-cells = <1>; 1128 #size-cells = <1>; 1129 ranges = <0 0x900 0x100>; 1130 1131 ducati_clkctrl: clk@20 { 1132 compatible = "ti,clkctrl"; 1133 reg = <0x20 0x4>; 1134 #clock-cells = <2>; 1135 }; 1136 }; 1137 1138 l3_dma_cm: l3_dma_cm@a00 { 1139 compatible = "ti,omap4-cm"; 1140 reg = <0xa00 0x100>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges = <0 0xa00 0x100>; 1144 1145 l3_dma_clkctrl: clk@20 { 1146 compatible = "ti,clkctrl"; 1147 reg = <0x20 0x4>; 1148 #clock-cells = <2>; 1149 }; 1150 }; 1151 1152 l3_emif_cm: l3_emif_cm@b00 { 1153 compatible = "ti,omap4-cm"; 1154 reg = <0xb00 0x100>; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 ranges = <0 0xb00 0x100>; 1158 1159 l3_emif_clkctrl: clk@20 { 1160 compatible = "ti,clkctrl"; 1161 reg = <0x20 0x1c>; 1162 #clock-cells = <2>; 1163 }; 1164 }; 1165 1166 d2d_cm: d2d_cm@c00 { 1167 compatible = "ti,omap4-cm"; 1168 reg = <0xc00 0x100>; 1169 #address-cells = <1>; 1170 #size-cells = <1>; 1171 ranges = <0 0xc00 0x100>; 1172 1173 d2d_clkctrl: clk@20 { 1174 compatible = "ti,clkctrl"; 1175 reg = <0x20 0x4>; 1176 #clock-cells = <2>; 1177 }; 1178 }; 1179 1180 l4_cfg_cm: l4_cfg_cm@d00 { 1181 compatible = "ti,omap4-cm"; 1182 reg = <0xd00 0x100>; 1183 #address-cells = <1>; 1184 #size-cells = <1>; 1185 ranges = <0 0xd00 0x100>; 1186 1187 l4_cfg_clkctrl: clk@20 { 1188 compatible = "ti,clkctrl"; 1189 reg = <0x20 0x14>; 1190 #clock-cells = <2>; 1191 }; 1192 }; 1193 1194 l3_instr_cm: l3_instr_cm@e00 { 1195 compatible = "ti,omap4-cm"; 1196 reg = <0xe00 0x100>; 1197 #address-cells = <1>; 1198 #size-cells = <1>; 1199 ranges = <0 0xe00 0x100>; 1200 1201 l3_instr_clkctrl: clk@20 { 1202 compatible = "ti,clkctrl"; 1203 reg = <0x20 0x24>; 1204 #clock-cells = <2>; 1205 }; 1206 }; 1207 1208 ivahd_cm: ivahd_cm@f00 { 1209 compatible = "ti,omap4-cm"; 1210 reg = <0xf00 0x100>; 1211 #address-cells = <1>; 1212 #size-cells = <1>; 1213 ranges = <0 0xf00 0x100>; 1214 1215 ivahd_clkctrl: clk@20 { 1216 compatible = "ti,clkctrl"; 1217 reg = <0x20 0xc>; 1218 #clock-cells = <2>; 1219 }; 1220 }; 1221 1222 iss_cm: iss_cm@1000 { 1223 compatible = "ti,omap4-cm"; 1224 reg = <0x1000 0x100>; 1225 #address-cells = <1>; 1226 #size-cells = <1>; 1227 ranges = <0 0x1000 0x100>; 1228 1229 iss_clkctrl: clk@20 { 1230 compatible = "ti,clkctrl"; 1231 reg = <0x20 0xc>; 1232 #clock-cells = <2>; 1233 }; 1234 }; 1235 1236 l3_dss_cm: l3_dss_cm@1100 { 1237 compatible = "ti,omap4-cm"; 1238 reg = <0x1100 0x100>; 1239 #address-cells = <1>; 1240 #size-cells = <1>; 1241 ranges = <0 0x1100 0x100>; 1242 1243 l3_dss_clkctrl: clk@20 { 1244 compatible = "ti,clkctrl"; 1245 reg = <0x20 0x4>; 1246 #clock-cells = <2>; 1247 }; 1248 }; 1249 1250 l3_gfx_cm: l3_gfx_cm@1200 { 1251 compatible = "ti,omap4-cm"; 1252 reg = <0x1200 0x100>; 1253 #address-cells = <1>; 1254 #size-cells = <1>; 1255 ranges = <0 0x1200 0x100>; 1256 1257 l3_gfx_clkctrl: clk@20 { 1258 compatible = "ti,clkctrl"; 1259 reg = <0x20 0x4>; 1260 #clock-cells = <2>; 1261 }; 1262 }; 1263 1264 l3_init_cm: l3_init_cm@1300 { 1265 compatible = "ti,omap4-cm"; 1266 reg = <0x1300 0x100>; 1267 #address-cells = <1>; 1268 #size-cells = <1>; 1269 ranges = <0 0x1300 0x100>; 1270 1271 l3_init_clkctrl: clk@20 { 1272 compatible = "ti,clkctrl"; 1273 reg = <0x20 0xc4>; 1274 #clock-cells = <2>; 1275 }; 1276 }; 1277 1278 l4_per_cm: l4_per_cm@1400 { 1279 compatible = "ti,omap4-cm"; 1280 reg = <0x1400 0x200>; 1281 #address-cells = <1>; 1282 #size-cells = <1>; 1283 ranges = <0 0x1400 0x200>; 1284 1285 l4_per_clkctrl: clk@20 { 1286 compatible = "ti,clkctrl"; 1287 reg = <0x20 0x144>; 1288 #clock-cells = <2>; 1289 }; 1290 }; 1291 1292}; 1293 1294&prm { 1295 l4_wkup_cm: l4_wkup_cm@1800 { 1296 compatible = "ti,omap4-cm"; 1297 reg = <0x1800 0x100>; 1298 #address-cells = <1>; 1299 #size-cells = <1>; 1300 ranges = <0 0x1800 0x100>; 1301 1302 l4_wkup_clkctrl: clk@20 { 1303 compatible = "ti,clkctrl"; 1304 reg = <0x20 0x5c>; 1305 #clock-cells = <2>; 1306 }; 1307 }; 1308 1309 emu_sys_cm: emu_sys_cm@1a00 { 1310 compatible = "ti,omap4-cm"; 1311 reg = <0x1a00 0x100>; 1312 #address-cells = <1>; 1313 #size-cells = <1>; 1314 ranges = <0 0x1a00 0x100>; 1315 1316 emu_sys_clkctrl: clk@20 { 1317 compatible = "ti,clkctrl"; 1318 reg = <0x20 0x4>; 1319 #clock-cells = <2>; 1320 }; 1321 }; 1322}; 1323
