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/Linux-v4.19/drivers/clk/renesas/
DMakefile7 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
16 obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
17 obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
[all …]
Dclk-sh73a0.c77 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
88 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
93 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
113 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
122 void __iomem *dsi_reg = cpg->reg + in sh73a0_cpg_register_clock()
159 cpg->reg + reg, shift, width, 0, in sh73a0_cpg_register_clock()
160 table, &cpg->lock); in sh73a0_cpg_register_clock()
166 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
177 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
179 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
[all …]
Dclk-r8a73a4.c63 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
74 u32 ckscr = readl(cpg->reg + CPG_CKSCR); in r8a73a4_cpg_register_clock()
98 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
105 u32 value = readl(cpg->reg + CPG_PLL1CR); in r8a73a4_cpg_register_clock()
128 value = readl(cpg->reg + cr); in r8a73a4_cpg_register_clock()
164 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock()
186 cpg->reg + reg, shift, 4, 0, in r8a73a4_cpg_register_clock()
187 table, &cpg->lock); in r8a73a4_cpg_register_clock()
193 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
204 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a73a4_cpg_clocks_init()
[all …]
Dclk-r8a7740.c65 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
101 u32 value = readl(cpg->reg + CPG_FRQCRC); in r8a7740_cpg_register_clock()
105 u32 value = readl(cpg->reg + CPG_FRQCRA); in r8a7740_cpg_register_clock()
110 u32 value = readl(cpg->reg + CPG_PLLC2CR); in r8a7740_cpg_register_clock()
114 u32 value = readl(cpg->reg + CPG_USBCKCR); in r8a7740_cpg_register_clock()
142 cpg->reg + reg, shift, 4, 0, in r8a7740_cpg_register_clock()
143 table, &cpg->lock); in r8a7740_cpg_register_clock()
149 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
163 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7740_cpg_clocks_init()
165 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
[all …]
Dclk-rz.c54 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) in rz_cpg_register_clock() argument
70 if (!cpg->reg) in rz_cpg_register_clock()
78 val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; in rz_cpg_register_clock()
80 val = readl(cpg->reg + CPG_FRQCR2) & 3; in rz_cpg_register_clock()
90 struct rz_cpg *cpg; in rz_cpg_clocks_init() local
99 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in rz_cpg_clocks_init()
101 BUG_ON(!cpg || !clks); in rz_cpg_clocks_init()
103 cpg->data.clks = clks; in rz_cpg_clocks_init()
104 cpg->data.clk_num = num_clks; in rz_cpg_clocks_init()
106 cpg->reg = of_iomap(np, 0); in rz_cpg_clocks_init()
[all …]
Dclk-rcar-gen2.c138 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) in cpg_z_clk_register() argument
155 zclk->reg = cpg->reg + CPG_FRQCRC; in cpg_z_clk_register()
156 zclk->kick_reg = cpg->reg + CPG_FRQCRB; in cpg_z_clk_register()
166 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, in cpg_rcan_clk_register() argument
187 gate->reg = cpg->reg + CPG_RCANCKCR; in cpg_rcan_clk_register()
190 gate->lock = &cpg->lock; in cpg_rcan_clk_register()
210 static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) in cpg_adsp_clk_register() argument
221 div->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
224 div->lock = &cpg->lock; in cpg_adsp_clk_register()
232 gate->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
[all …]
Dclk-r8a7778.c53 r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, in r8a7778_cpg_register_clock() argument
83 struct r8a7778_cpg *cpg; in r8a7778_cpg_clocks_init() local
106 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7778_cpg_clocks_init()
108 if (cpg == NULL || clks == NULL) { in r8a7778_cpg_clocks_init()
115 spin_lock_init(&cpg->lock); in r8a7778_cpg_clocks_init()
117 cpg->data.clks = clks; in r8a7778_cpg_clocks_init()
118 cpg->data.clk_num = num_clks; in r8a7778_cpg_clocks_init()
120 cpg->reg = of_iomap(np, 0); in r8a7778_cpg_clocks_init()
121 if (WARN_ON(cpg->reg == NULL)) in r8a7778_cpg_clocks_init()
131 clk = r8a7778_cpg_register_clock(np, cpg, name); in r8a7778_cpg_clocks_init()
[all …]
Dclk-r8a7779.c93 r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, in r8a7779_cpg_register_clock() argument
125 struct r8a7779_cpg *cpg; in r8a7779_cpg_clocks_init() local
140 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7779_cpg_clocks_init()
142 if (cpg == NULL || clks == NULL) { in r8a7779_cpg_clocks_init()
149 spin_lock_init(&cpg->lock); in r8a7779_cpg_clocks_init()
151 cpg->data.clks = clks; in r8a7779_cpg_clocks_init()
152 cpg->data.clk_num = num_clks; in r8a7779_cpg_clocks_init()
164 clk = r8a7779_cpg_register_clock(np, cpg, config, in r8a7779_cpg_clocks_init()
170 cpg->data.clks[i] = clk; in r8a7779_cpg_clocks_init()
173 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); in r8a7779_cpg_clocks_init()
/Linux-v4.19/arch/arm/boot/dts/
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
64 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
112 clocks = <&cpg CPG_MOD 402>;
114 resets = <&cpg 402>;
128 clocks = <&cpg CPG_MOD 912>;
130 resets = <&cpg 912>;
143 clocks = <&cpg CPG_MOD 911>;
145 resets = <&cpg 911>;
158 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
170 resets = <&cpg 910>;
183 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
130 clocks = <&cpg CPG_MOD 402>;
132 resets = <&cpg 402>;
146 clocks = <&cpg CPG_MOD 912>;
148 resets = <&cpg 912>;
161 clocks = <&cpg CPG_MOD 911>;
163 resets = <&cpg 911>;
176 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
97 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
167 clocks = <&cpg CPG_MOD 912>;
169 resets = <&cpg 912>;
182 clocks = <&cpg CPG_MOD 911>;
184 resets = <&cpg 911>;
197 clocks = <&cpg CPG_MOD 910>;
199 resets = <&cpg 910>;
212 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
121 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
163 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
185 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
196 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
270 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
25 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
63 cpg: clock-controller@e6150000 { label
64 compatible = "renesas,r8a77470-cpg-mssr";
99 clocks = <&cpg CPG_MOD 407>;
101 resets = <&cpg 407>;
152 clocks = <&cpg CPG_MOD 219>;
155 resets = <&cpg 219>;
185 clocks = <&cpg CPG_MOD 218>;
188 resets = <&cpg 218>;
[all …]
/Linux-v4.19/arch/arm64/boot/dts/renesas/
Dr8a7796.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
137 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
149 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
161 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
172 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
183 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
273 clocks = <&cpg CPG_MOD 402>;
275 resets = <&cpg 402>;
289 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a7795.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
126 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
138 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
150 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
162 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
174 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
185 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
196 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
207 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
294 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
145 clocks = <&cpg CPG_MOD 402>;
147 resets = <&cpg 402>;
161 clocks = <&cpg CPG_MOD 912>;
163 resets = <&cpg 912>;
176 clocks = <&cpg CPG_MOD 911>;
178 resets = <&cpg 911>;
191 clocks = <&cpg CPG_MOD 910>;
193 resets = <&cpg 910>;
206 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
36 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
46 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
56 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
66 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
131 clocks = <&cpg CPG_MOD 912>;
133 resets = <&cpg 912>;
146 clocks = <&cpg CPG_MOD 911>;
148 resets = <&cpg 911>;
161 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77970.dtsi9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
111 clocks = <&cpg CPG_MOD 402>;
113 resets = <&cpg 402>;
127 clocks = <&cpg CPG_MOD 912>;
129 resets = <&cpg 912>;
142 clocks = <&cpg CPG_MOD 911>;
144 resets = <&cpg 911>;
157 clocks = <&cpg CPG_MOD 910>;
[all …]
Dulcb.dtsi372 clocks = <&cpg CPG_MOD 1005>,
373 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
374 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
375 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
376 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
377 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
378 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
379 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
380 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
381 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
77 clocks = <&cpg CPG_MOD 402>;
79 resets = <&cpg 402>;
93 clocks = <&cpg CPG_MOD 912>;
95 resets = <&cpg 912>;
108 clocks = <&cpg CPG_MOD 911>;
110 resets = <&cpg 911>;
123 clocks = <&cpg CPG_MOD 910>;
125 resets = <&cpg 910>;
138 clocks = <&cpg CPG_MOD 909>;
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.txt16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
19 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
20 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
21 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
22 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
23 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
24 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
25 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
[all …]

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