1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a7792 SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 spi0 = &qspi; 26 spi1 = &msiof0; 27 spi2 = &msiof1; 28 vin0 = &vin0; 29 vin1 = &vin1; 30 vin2 = &vin2; 31 vin3 = &vin3; 32 vin4 = &vin4; 33 vin5 = &vin5; 34 }; 35 36 /* External CAN clock */ 37 can_clk: can { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 /* This value must be overridden by the board. */ 41 clock-frequency = <0>; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "renesas,apmu"; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a15"; 52 reg = <0>; 53 clock-frequency = <1000000000>; 54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 56 next-level-cache = <&L2_CA15>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a15"; 62 reg = <1>; 63 clock-frequency = <1000000000>; 64 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 65 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 66 next-level-cache = <&L2_CA15>; 67 }; 68 69 L2_CA15: cache-controller-0 { 70 compatible = "cache"; 71 cache-unified; 72 cache-level = <2>; 73 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 74 }; 75 }; 76 77 /* External root clock */ 78 extal_clk: extal { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 /* This value must be overridden by the board. */ 82 clock-frequency = <0>; 83 }; 84 85 pmu { 86 compatible = "arm,cortex-a15-pmu"; 87 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 88 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 89 interrupt-affinity = <&cpu0>, <&cpu1>; 90 }; 91 92 /* External SCIF clock */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 /* This value must be overridden by the board. */ 97 clock-frequency = <0>; 98 }; 99 100 soc { 101 compatible = "simple-bus"; 102 interrupt-parent = <&gic>; 103 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 rwdt: watchdog@e6020000 { 109 compatible = "renesas,r8a7792-wdt", 110 "renesas,rcar-gen2-wdt"; 111 reg = <0 0xe6020000 0 0x0c>; 112 clocks = <&cpg CPG_MOD 402>; 113 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 114 resets = <&cpg 402>; 115 status = "disabled"; 116 }; 117 118 gpio0: gpio@e6050000 { 119 compatible = "renesas,gpio-r8a7792", 120 "renesas,rcar-gen2-gpio"; 121 reg = <0 0xe6050000 0 0x50>; 122 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 123 #gpio-cells = <2>; 124 gpio-controller; 125 gpio-ranges = <&pfc 0 0 29>; 126 #interrupt-cells = <2>; 127 interrupt-controller; 128 clocks = <&cpg CPG_MOD 912>; 129 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 130 resets = <&cpg 912>; 131 }; 132 133 gpio1: gpio@e6051000 { 134 compatible = "renesas,gpio-r8a7792", 135 "renesas,rcar-gen2-gpio"; 136 reg = <0 0xe6051000 0 0x50>; 137 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 138 #gpio-cells = <2>; 139 gpio-controller; 140 gpio-ranges = <&pfc 0 32 23>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 clocks = <&cpg CPG_MOD 911>; 144 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 145 resets = <&cpg 911>; 146 }; 147 148 gpio2: gpio@e6052000 { 149 compatible = "renesas,gpio-r8a7792", 150 "renesas,rcar-gen2-gpio"; 151 reg = <0 0xe6052000 0 0x50>; 152 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 64 32>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&cpg CPG_MOD 910>; 159 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 160 resets = <&cpg 910>; 161 }; 162 163 gpio3: gpio@e6053000 { 164 compatible = "renesas,gpio-r8a7792", 165 "renesas,rcar-gen2-gpio"; 166 reg = <0 0xe6053000 0 0x50>; 167 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 96 28>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 909>; 174 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 175 resets = <&cpg 909>; 176 }; 177 178 gpio4: gpio@e6054000 { 179 compatible = "renesas,gpio-r8a7792", 180 "renesas,rcar-gen2-gpio"; 181 reg = <0 0xe6054000 0 0x50>; 182 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 128 17>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 908>; 189 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 190 resets = <&cpg 908>; 191 }; 192 193 gpio5: gpio@e6055000 { 194 compatible = "renesas,gpio-r8a7792", 195 "renesas,rcar-gen2-gpio"; 196 reg = <0 0xe6055000 0 0x50>; 197 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 160 17>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 907>; 204 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 205 resets = <&cpg 907>; 206 }; 207 208 gpio6: gpio@e6055100 { 209 compatible = "renesas,gpio-r8a7792", 210 "renesas,rcar-gen2-gpio"; 211 reg = <0 0xe6055100 0 0x50>; 212 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 213 #gpio-cells = <2>; 214 gpio-controller; 215 gpio-ranges = <&pfc 0 192 17>; 216 #interrupt-cells = <2>; 217 interrupt-controller; 218 clocks = <&cpg CPG_MOD 905>; 219 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 220 resets = <&cpg 905>; 221 }; 222 223 gpio7: gpio@e6055200 { 224 compatible = "renesas,gpio-r8a7792", 225 "renesas,rcar-gen2-gpio"; 226 reg = <0 0xe6055200 0 0x50>; 227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 228 #gpio-cells = <2>; 229 gpio-controller; 230 gpio-ranges = <&pfc 0 224 17>; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 clocks = <&cpg CPG_MOD 904>; 234 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 235 resets = <&cpg 904>; 236 }; 237 238 gpio8: gpio@e6055300 { 239 compatible = "renesas,gpio-r8a7792", 240 "renesas,rcar-gen2-gpio"; 241 reg = <0 0xe6055300 0 0x50>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 #gpio-cells = <2>; 244 gpio-controller; 245 gpio-ranges = <&pfc 0 256 17>; 246 #interrupt-cells = <2>; 247 interrupt-controller; 248 clocks = <&cpg CPG_MOD 921>; 249 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 250 resets = <&cpg 921>; 251 }; 252 253 gpio9: gpio@e6055400 { 254 compatible = "renesas,gpio-r8a7792", 255 "renesas,rcar-gen2-gpio"; 256 reg = <0 0xe6055400 0 0x50>; 257 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 gpio-ranges = <&pfc 0 288 17>; 261 #interrupt-cells = <2>; 262 interrupt-controller; 263 clocks = <&cpg CPG_MOD 919>; 264 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 265 resets = <&cpg 919>; 266 }; 267 268 gpio10: gpio@e6055500 { 269 compatible = "renesas,gpio-r8a7792", 270 "renesas,rcar-gen2-gpio"; 271 reg = <0 0xe6055500 0 0x50>; 272 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 273 #gpio-cells = <2>; 274 gpio-controller; 275 gpio-ranges = <&pfc 0 320 32>; 276 #interrupt-cells = <2>; 277 interrupt-controller; 278 clocks = <&cpg CPG_MOD 914>; 279 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 280 resets = <&cpg 914>; 281 }; 282 283 gpio11: gpio@e6055600 { 284 compatible = "renesas,gpio-r8a7792", 285 "renesas,rcar-gen2-gpio"; 286 reg = <0 0xe6055600 0 0x50>; 287 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 288 #gpio-cells = <2>; 289 gpio-controller; 290 gpio-ranges = <&pfc 0 352 30>; 291 #interrupt-cells = <2>; 292 interrupt-controller; 293 clocks = <&cpg CPG_MOD 913>; 294 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 295 resets = <&cpg 913>; 296 }; 297 298 pfc: pin-controller@e6060000 { 299 compatible = "renesas,pfc-r8a7792"; 300 reg = <0 0xe6060000 0 0x144>; 301 }; 302 303 cpg: clock-controller@e6150000 { 304 compatible = "renesas,r8a7792-cpg-mssr"; 305 reg = <0 0xe6150000 0 0x1000>; 306 clocks = <&extal_clk>; 307 clock-names = "extal"; 308 #clock-cells = <2>; 309 #power-domain-cells = <0>; 310 #reset-cells = <1>; 311 }; 312 313 apmu@e6152000 { 314 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 315 reg = <0 0xe6152000 0 0x188>; 316 cpus = <&cpu0 &cpu1>; 317 }; 318 319 rst: reset-controller@e6160000 { 320 compatible = "renesas,r8a7792-rst"; 321 reg = <0 0xe6160000 0 0x0100>; 322 }; 323 324 sysc: system-controller@e6180000 { 325 compatible = "renesas,r8a7792-sysc"; 326 reg = <0 0xe6180000 0 0x0200>; 327 #power-domain-cells = <1>; 328 }; 329 330 irqc: interrupt-controller@e61c0000 { 331 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 332 #interrupt-cells = <2>; 333 interrupt-controller; 334 reg = <0 0xe61c0000 0 0x200>; 335 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cpg CPG_MOD 407>; 340 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 341 resets = <&cpg 407>; 342 }; 343 344 icram0: sram@e63a0000 { 345 compatible = "mmio-sram"; 346 reg = <0 0xe63a0000 0 0x12000>; 347 }; 348 349 icram1: sram@e63c0000 { 350 compatible = "mmio-sram"; 351 reg = <0 0xe63c0000 0 0x1000>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0 0 0xe63c0000 0x1000>; 355 356 smp-sram@0 { 357 compatible = "renesas,smp-sram"; 358 reg = <0 0x100>; 359 }; 360 }; 361 362 /* I2C doesn't need pinmux */ 363 i2c0: i2c@e6508000 { 364 compatible = "renesas,i2c-r8a7792", 365 "renesas,rcar-gen2-i2c"; 366 reg = <0 0xe6508000 0 0x40>; 367 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&cpg CPG_MOD 931>; 369 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 370 resets = <&cpg 931>; 371 i2c-scl-internal-delay-ns = <6>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 i2c1: i2c@e6518000 { 378 compatible = "renesas,i2c-r8a7792", 379 "renesas,rcar-gen2-i2c"; 380 reg = <0 0xe6518000 0 0x40>; 381 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cpg CPG_MOD 930>; 383 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 384 resets = <&cpg 930>; 385 i2c-scl-internal-delay-ns = <6>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 status = "disabled"; 389 }; 390 391 i2c2: i2c@e6530000 { 392 compatible = "renesas,i2c-r8a7792", 393 "renesas,rcar-gen2-i2c"; 394 reg = <0 0xe6530000 0 0x40>; 395 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cpg CPG_MOD 929>; 397 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 398 resets = <&cpg 929>; 399 i2c-scl-internal-delay-ns = <6>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2c3: i2c@e6540000 { 406 compatible = "renesas,i2c-r8a7792", 407 "renesas,rcar-gen2-i2c"; 408 reg = <0 0xe6540000 0 0x40>; 409 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 928>; 411 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 412 resets = <&cpg 928>; 413 i2c-scl-internal-delay-ns = <6>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 419 i2c4: i2c@e6520000 { 420 compatible = "renesas,i2c-r8a7792", 421 "renesas,rcar-gen2-i2c"; 422 reg = <0 0xe6520000 0 0x40>; 423 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&cpg CPG_MOD 927>; 425 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 426 resets = <&cpg 927>; 427 i2c-scl-internal-delay-ns = <6>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 status = "disabled"; 431 }; 432 433 i2c5: i2c@e6528000 { 434 compatible = "renesas,i2c-r8a7792", 435 "renesas,rcar-gen2-i2c"; 436 reg = <0 0xe6528000 0 0x40>; 437 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 925>; 439 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 440 resets = <&cpg 925>; 441 i2c-scl-internal-delay-ns = <110>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 dmac0: dma-controller@e6700000 { 448 compatible = "renesas,dmac-r8a7792", 449 "renesas,rcar-dmac"; 450 reg = <0 0xe6700000 0 0x20000>; 451 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 452 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 453 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 454 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 455 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 456 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 457 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 458 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 459 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 460 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 461 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 462 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 463 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 464 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 465 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 466 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "error", 468 "ch0", "ch1", "ch2", "ch3", 469 "ch4", "ch5", "ch6", "ch7", 470 "ch8", "ch9", "ch10", "ch11", 471 "ch12", "ch13", "ch14"; 472 clocks = <&cpg CPG_MOD 219>; 473 clock-names = "fck"; 474 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 475 resets = <&cpg 219>; 476 #dma-cells = <1>; 477 dma-channels = <15>; 478 }; 479 480 dmac1: dma-controller@e6720000 { 481 compatible = "renesas,dmac-r8a7792", 482 "renesas,rcar-dmac"; 483 reg = <0 0xe6720000 0 0x20000>; 484 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 485 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 486 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 487 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 489 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 490 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 491 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 492 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 493 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 494 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 495 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 496 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 497 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 498 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 499 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 500 interrupt-names = "error", 501 "ch0", "ch1", "ch2", "ch3", 502 "ch4", "ch5", "ch6", "ch7", 503 "ch8", "ch9", "ch10", "ch11", 504 "ch12", "ch13", "ch14"; 505 clocks = <&cpg CPG_MOD 218>; 506 clock-names = "fck"; 507 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 508 resets = <&cpg 218>; 509 #dma-cells = <1>; 510 dma-channels = <15>; 511 }; 512 513 avb: ethernet@e6800000 { 514 compatible = "renesas,etheravb-r8a7792", 515 "renesas,etheravb-rcar-gen2"; 516 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 517 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cpg CPG_MOD 812>; 519 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 520 resets = <&cpg 812>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 qspi: spi@e6b10000 { 527 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 528 reg = <0 0xe6b10000 0 0x2c>; 529 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cpg CPG_MOD 917>; 531 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 532 <&dmac1 0x17>, <&dmac1 0x18>; 533 dma-names = "tx", "rx", "tx", "rx"; 534 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 535 resets = <&cpg 917>; 536 num-cs = <1>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 status = "disabled"; 540 }; 541 542 scif0: serial@e6e60000 { 543 compatible = "renesas,scif-r8a7792", 544 "renesas,rcar-gen2-scif", "renesas,scif"; 545 reg = <0 0xe6e60000 0 64>; 546 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cpg CPG_MOD 721>, 548 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 549 clock-names = "fck", "brg_int", "scif_clk"; 550 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 551 <&dmac1 0x29>, <&dmac1 0x2a>; 552 dma-names = "tx", "rx", "tx", "rx"; 553 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 554 resets = <&cpg 721>; 555 status = "disabled"; 556 }; 557 558 scif1: serial@e6e68000 { 559 compatible = "renesas,scif-r8a7792", 560 "renesas,rcar-gen2-scif", "renesas,scif"; 561 reg = <0 0xe6e68000 0 64>; 562 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cpg CPG_MOD 720>, 564 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 565 clock-names = "fck", "brg_int", "scif_clk"; 566 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 567 <&dmac1 0x2d>, <&dmac1 0x2e>; 568 dma-names = "tx", "rx", "tx", "rx"; 569 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 570 resets = <&cpg 720>; 571 status = "disabled"; 572 }; 573 574 scif2: serial@e6e58000 { 575 compatible = "renesas,scif-r8a7792", 576 "renesas,rcar-gen2-scif", "renesas,scif"; 577 reg = <0 0xe6e58000 0 64>; 578 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cpg CPG_MOD 719>, 580 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 581 clock-names = "fck", "brg_int", "scif_clk"; 582 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 583 <&dmac1 0x2b>, <&dmac1 0x2c>; 584 dma-names = "tx", "rx", "tx", "rx"; 585 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 586 resets = <&cpg 719>; 587 status = "disabled"; 588 }; 589 590 scif3: serial@e6ea8000 { 591 compatible = "renesas,scif-r8a7792", 592 "renesas,rcar-gen2-scif", "renesas,scif"; 593 reg = <0 0xe6ea8000 0 64>; 594 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 718>, 596 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 597 clock-names = "fck", "brg_int", "scif_clk"; 598 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 599 <&dmac1 0x2f>, <&dmac1 0x30>; 600 dma-names = "tx", "rx", "tx", "rx"; 601 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 602 resets = <&cpg 718>; 603 status = "disabled"; 604 }; 605 606 hscif0: serial@e62c0000 { 607 compatible = "renesas,hscif-r8a7792", 608 "renesas,rcar-gen2-hscif", "renesas,hscif"; 609 reg = <0 0xe62c0000 0 96>; 610 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 717>, 612 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 613 clock-names = "fck", "brg_int", "scif_clk"; 614 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 615 <&dmac1 0x39>, <&dmac1 0x3a>; 616 dma-names = "tx", "rx", "tx", "rx"; 617 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 618 resets = <&cpg 717>; 619 status = "disabled"; 620 }; 621 622 hscif1: serial@e62c8000 { 623 compatible = "renesas,hscif-r8a7792", 624 "renesas,rcar-gen2-hscif", "renesas,hscif"; 625 reg = <0 0xe62c8000 0 96>; 626 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cpg CPG_MOD 716>, 628 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 629 clock-names = "fck", "brg_int", "scif_clk"; 630 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 631 <&dmac1 0x4d>, <&dmac1 0x4e>; 632 dma-names = "tx", "rx", "tx", "rx"; 633 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 634 resets = <&cpg 716>; 635 status = "disabled"; 636 }; 637 638 msiof0: spi@e6e20000 { 639 compatible = "renesas,msiof-r8a7792", 640 "renesas,rcar-gen2-msiof"; 641 reg = <0 0xe6e20000 0 0x0064>; 642 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cpg CPG_MOD 000>; 644 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 645 <&dmac1 0x51>, <&dmac1 0x52>; 646 dma-names = "tx", "rx", "tx", "rx"; 647 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 648 resets = <&cpg 000>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 status = "disabled"; 652 }; 653 654 msiof1: spi@e6e10000 { 655 compatible = "renesas,msiof-r8a7792", 656 "renesas,rcar-gen2-msiof"; 657 reg = <0 0xe6e10000 0 0x0064>; 658 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cpg CPG_MOD 208>; 660 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 661 <&dmac1 0x55>, <&dmac1 0x56>; 662 dma-names = "tx", "rx", "tx", "rx"; 663 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 664 resets = <&cpg 208>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 status = "disabled"; 668 }; 669 670 can0: can@e6e80000 { 671 compatible = "renesas,can-r8a7792", 672 "renesas,rcar-gen2-can"; 673 reg = <0 0xe6e80000 0 0x1000>; 674 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cpg CPG_MOD 916>, 676 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 677 clock-names = "clkp1", "clkp2", "can_clk"; 678 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 679 resets = <&cpg 916>; 680 status = "disabled"; 681 }; 682 683 can1: can@e6e88000 { 684 compatible = "renesas,can-r8a7792", 685 "renesas,rcar-gen2-can"; 686 reg = <0 0xe6e88000 0 0x1000>; 687 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 915>, 689 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 690 clock-names = "clkp1", "clkp2", "can_clk"; 691 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 692 resets = <&cpg 915>; 693 status = "disabled"; 694 }; 695 696 vin0: video@e6ef0000 { 697 compatible = "renesas,vin-r8a7792", 698 "renesas,rcar-gen2-vin"; 699 reg = <0 0xe6ef0000 0 0x1000>; 700 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 811>; 702 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 703 resets = <&cpg 811>; 704 status = "disabled"; 705 }; 706 707 vin1: video@e6ef1000 { 708 compatible = "renesas,vin-r8a7792", 709 "renesas,rcar-gen2-vin"; 710 reg = <0 0xe6ef1000 0 0x1000>; 711 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cpg CPG_MOD 810>; 713 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 714 resets = <&cpg 810>; 715 status = "disabled"; 716 }; 717 718 vin2: video@e6ef2000 { 719 compatible = "renesas,vin-r8a7792", 720 "renesas,rcar-gen2-vin"; 721 reg = <0 0xe6ef2000 0 0x1000>; 722 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 809>; 724 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 725 resets = <&cpg 809>; 726 status = "disabled"; 727 }; 728 729 vin3: video@e6ef3000 { 730 compatible = "renesas,vin-r8a7792", 731 "renesas,rcar-gen2-vin"; 732 reg = <0 0xe6ef3000 0 0x1000>; 733 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cpg CPG_MOD 808>; 735 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 736 resets = <&cpg 808>; 737 status = "disabled"; 738 }; 739 740 vin4: video@e6ef4000 { 741 compatible = "renesas,vin-r8a7792", 742 "renesas,rcar-gen2-vin"; 743 reg = <0 0xe6ef4000 0 0x1000>; 744 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&cpg CPG_MOD 805>; 746 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 747 resets = <&cpg 805>; 748 status = "disabled"; 749 }; 750 751 vin5: video@e6ef5000 { 752 compatible = "renesas,vin-r8a7792", 753 "renesas,rcar-gen2-vin"; 754 reg = <0 0xe6ef5000 0 0x1000>; 755 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cpg CPG_MOD 804>; 757 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 758 resets = <&cpg 804>; 759 status = "disabled"; 760 }; 761 762 sdhi0: sd@ee100000 { 763 compatible = "renesas,sdhi-r8a7792", 764 "renesas,rcar-gen2-sdhi"; 765 reg = <0 0xee100000 0 0x328>; 766 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 767 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 768 <&dmac1 0xcd>, <&dmac1 0xce>; 769 dma-names = "tx", "rx", "tx", "rx"; 770 clocks = <&cpg CPG_MOD 314>; 771 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 772 resets = <&cpg 314>; 773 status = "disabled"; 774 }; 775 776 gic: interrupt-controller@f1001000 { 777 compatible = "arm,gic-400"; 778 #interrupt-cells = <3>; 779 interrupt-controller; 780 reg = <0 0xf1001000 0 0x1000>, 781 <0 0xf1002000 0 0x2000>, 782 <0 0xf1004000 0 0x2000>, 783 <0 0xf1006000 0 0x2000>; 784 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 785 IRQ_TYPE_LEVEL_HIGH)>; 786 clocks = <&cpg CPG_MOD 408>; 787 clock-names = "clk"; 788 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 789 resets = <&cpg 408>; 790 }; 791 792 vsp@fe928000 { 793 compatible = "renesas,vsp1"; 794 reg = <0 0xfe928000 0 0x8000>; 795 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 131>; 797 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 798 resets = <&cpg 131>; 799 }; 800 801 vsp@fe930000 { 802 compatible = "renesas,vsp1"; 803 reg = <0 0xfe930000 0 0x8000>; 804 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cpg CPG_MOD 128>; 806 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 807 resets = <&cpg 128>; 808 }; 809 810 vsp@fe938000 { 811 compatible = "renesas,vsp1"; 812 reg = <0 0xfe938000 0 0x8000>; 813 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cpg CPG_MOD 127>; 815 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 816 resets = <&cpg 127>; 817 }; 818 819 jpu: jpeg-codec@fe980000 { 820 compatible = "renesas,jpu-r8a7792", 821 "renesas,rcar-gen2-jpu"; 822 reg = <0 0xfe980000 0 0x10300>; 823 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 106>; 825 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 826 resets = <&cpg 106>; 827 }; 828 829 du: display@feb00000 { 830 compatible = "renesas,du-r8a7792"; 831 reg = <0 0xfeb00000 0 0x40000>; 832 reg-names = "du"; 833 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 724>, 836 <&cpg CPG_MOD 723>; 837 clock-names = "du.0", "du.1"; 838 status = "disabled"; 839 840 ports { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 844 port@0 { 845 reg = <0>; 846 du_out_rgb0: endpoint { 847 }; 848 }; 849 port@1 { 850 reg = <1>; 851 du_out_rgb1: endpoint { 852 }; 853 }; 854 }; 855 }; 856 857 prr: chipid@ff000044 { 858 compatible = "renesas,prr"; 859 reg = <0 0xff000044 0 4>; 860 }; 861 }; 862 863 timer { 864 compatible = "arm,armv7-timer"; 865 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 866 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 867 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 868 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 869 }; 870}; 871
