1* Renesas Clock Pulse Generator / Module Standby and Software Reset
2
3On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
4and MSSR (Module Standby and Software Reset) blocks are intimately connected,
5and share the same register block.
6
7They provide the following functionalities:
8  - The CPG block generates various core clocks,
9  - The MSSR block provides two functions:
10      1. Module Standby, providing a Clock Domain to control the clock supply
11	 to individual SoC devices,
12      2. Reset Control, to perform a software reset of individual SoC devices.
13
14Required Properties:
15  - compatible: Must be one of:
16      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
19      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
20      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
21      - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
22      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
23      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
24      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
25      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
26      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
27      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
28      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
29      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
30      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
31
32  - reg: Base address and length of the memory resource used by the CPG/MSSR
33    block
34
35  - clocks: References to external parent clocks, one entry for each entry in
36    clock-names
37  - clock-names: List of external parent clock names. Valid names are:
38      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
39		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
40		 r8a77980, r8a77990, r8a77995)
41      - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
42      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
43		     r8a7794)
44
45  - #clock-cells: Must be 2
46      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
47	and a core clock reference, as defined in
48	<dt-bindings/clock/*-cpg-mssr.h>.
49      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
50	a module number, as defined in the datasheet.
51
52  - #power-domain-cells: Must be 0
53      - SoC devices that are part of the CPG/MSSR Clock Domain and can be
54	power-managed through Module Standby should refer to the CPG device
55	node in their "power-domains" property, as documented by the generic PM
56	Domain bindings in
57	Documentation/devicetree/bindings/power/power_domain.txt.
58
59  - #reset-cells: Must be 1
60      - The single reset specifier cell must be the module number, as defined
61	in the datasheet.
62
63
64Examples
65--------
66
67  - CPG device node:
68
69	cpg: clock-controller@e6150000 {
70		compatible = "renesas,r8a7795-cpg-mssr";
71		reg = <0 0xe6150000 0 0x1000>;
72		clocks = <&extal_clk>, <&extalr_clk>;
73		clock-names = "extal", "extalr";
74		#clock-cells = <2>;
75		#power-domain-cells = <0>;
76		#reset-cells = <1>;
77	};
78
79
80  - CPG/MSSR Clock Domain member device node:
81
82	scif2: serial@e6e88000 {
83		compatible = "renesas,scif-r8a7795", "renesas,scif";
84		reg = <0 0xe6e88000 0 64>;
85		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
86		clocks = <&cpg CPG_MOD 310>;
87		clock-names = "fck";
88		dmas = <&dmac1 0x13>, <&dmac1 0x12>;
89		dma-names = "tx", "rx";
90		power-domains = <&cpg>;
91		resets = <&cpg 310>;
92	};
93