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Searched refs:clks (Results 1 – 25 of 452) sorted by relevance

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/Linux-v4.19/drivers/clk/imx/
Dclk-imx7d.c48 static struct clk *clks[IMX7D_CLK_END]; variable
393 &clks[IMX7D_UART1_ROOT_CLK],
394 &clks[IMX7D_UART2_ROOT_CLK],
395 &clks[IMX7D_UART3_ROOT_CLK],
396 &clks[IMX7D_UART4_ROOT_CLK],
397 &clks[IMX7D_UART5_ROOT_CLK],
398 &clks[IMX7D_UART6_ROOT_CLK],
399 &clks[IMX7D_UART7_ROOT_CLK],
409 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx7d_clocks_init()
410 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); in imx7d_clocks_init()
[all …]
Dclk-imx6sx.c92 static struct clk *clks[IMX6SX_CLK_CLK_END]; variable
128 &clks[IMX6SX_CLK_UART_IPG],
129 &clks[IMX6SX_CLK_UART_SERIAL],
138 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sx_clocks_init()
140 clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
141 clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6sx_clocks_init()
144 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
145 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
148 clks[IMX6SX_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1"); in imx6sx_clocks_init()
149 clks[IMX6SX_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2"); in imx6sx_clocks_init()
[all …]
Dclk-imx6ul.c79 static struct clk *clks[IMX6UL_CLK_END]; variable
127 clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6ul_clocks_init()
129 clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6ul_clocks_init()
130 clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6ul_clocks_init()
133 clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
134 clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
141 …clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
142 …clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
143 …clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
144 …clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
[all …]
Dclk-imx6sll.c56 static struct clk *clks[IMX6SLL_CLK_END]; variable
84 clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sll_clocks_init()
86 clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6sll_clocks_init()
87 clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6sll_clocks_init()
90 clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6sll_clocks_init()
91 clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6sll_clocks_init()
107 …clks[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_… in imx6sll_clocks_init()
108 …clks[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_… in imx6sll_clocks_init()
109 …clks[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_… in imx6sll_clocks_init()
110 …clks[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_… in imx6sll_clocks_init()
[all …]
Dclk-imx6sl.c102 static struct clk *clks[IMX6SL_CLK_END]; variable
185 &clks[IMX6SL_CLK_UART],
186 &clks[IMX6SL_CLK_UART_SERIAL],
196 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sl_clocks_init()
197 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6sl_clocks_init()
198 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6sl_clocks_init()
200 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sl_clocks_init()
207 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
208 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
209 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
/Linux-v4.19/drivers/clk/hisilicon/
Dclk.c65 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
94 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
105 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
112 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
113 clks[i].parent_name, in hisi_clk_register_fixed_rate()
114 clks[i].flags, in hisi_clk_register_fixed_rate()
115 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
118 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
121 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
128 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
[all …]
/Linux-v4.19/drivers/clk/mmp/
Dclk.c21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
[all …]
/Linux-v4.19/drivers/clk/mxs/
Dclk-imx28.c151 static struct clk *clks[clk_max]; variable
173 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
177 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
178 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
179 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
180 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
181 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
[all …]
Dclk-imx23.c96 static struct clk *clks[clk_max]; variable
118 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
119 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
120 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
121 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
122 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
123 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
124 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
125 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
126 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
/Linux-v4.19/drivers/clk/socfpga/
Dclk-s10.c168 static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, in s10_clk_register_c_perip() argument
176 clk = s10_register_periph(clks[i].name, clks[i].parent_name, in s10_clk_register_c_perip()
177 clks[i].parent_names, clks[i].num_parents, in s10_clk_register_c_perip()
178 clks[i].flags, base, clks[i].offset); in s10_clk_register_c_perip()
181 __func__, clks[i].name); in s10_clk_register_c_perip()
184 data->clk_data.clks[clks[i].id] = clk; in s10_clk_register_c_perip()
189 static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, in s10_clk_register_cnt_perip() argument
197 clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name, in s10_clk_register_cnt_perip()
198 clks[i].parent_names, in s10_clk_register_cnt_perip()
199 clks[i].num_parents, in s10_clk_register_cnt_perip()
[all …]
/Linux-v4.19/drivers/clk/
Dclk-bulk.c23 void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) in clk_bulk_put() argument
26 clk_put(clks[num_clks].clk); in clk_bulk_put()
27 clks[num_clks].clk = NULL; in clk_bulk_put()
33 struct clk_bulk_data *clks) in clk_bulk_get() argument
39 clks[i].clk = NULL; in clk_bulk_get()
42 clks[i].clk = clk_get(dev, clks[i].id); in clk_bulk_get()
43 if (IS_ERR(clks[i].clk)) { in clk_bulk_get()
44 ret = PTR_ERR(clks[i].clk); in clk_bulk_get()
47 clks[i].id, ret); in clk_bulk_get()
48 clks[i].clk = NULL; in clk_bulk_get()
[all …]
/Linux-v4.19/arch/powerpc/platforms/512x/
Dclock-commonclk.c74 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
404 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
405 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
447 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
448 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
462 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
651 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
652 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
675 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
682 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/Linux-v4.19/drivers/clk/axis/
Dclk-artpec6.c46 struct clk **clks; in of_artpec6_clkctrl_setup() local
59 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
62 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
91 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
95 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
97 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
101 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
103 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
107 clks[ARTPEC6_CLK_DBG_PCLK] = in of_artpec6_clkctrl_setup()
[all …]
/Linux-v4.19/arch/arm/boot/dts/
Dimx27.dtsi74 clocks = <&clks IMX27_CLK_CPU_DIV>;
97 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
98 <&clks IMX27_CLK_DMA_AHB_GATE>;
108 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
115 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
116 <&clks IMX27_CLK_PER1_GATE>;
124 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
125 <&clks IMX27_CLK_PER1_GATE>;
133 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
134 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx6qdl.dtsi79 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
159 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
170 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
171 <&clks IMX6QDL_CLK_GPMI_APB>,
172 <&clks IMX6QDL_CLK_GPMI_BCH>,
173 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
174 <&clks IMX6QDL_CLK_PER1_BCH>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
214 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
[all …]
Dimx6sx.dtsi83 clocks = <&clks IMX6SX_CLK_ARM>,
84 <&clks IMX6SX_CLK_PLL2_PFD2>,
85 <&clks IMX6SX_CLK_STEP>,
86 <&clks IMX6SX_CLK_PLL1_SW>,
87 <&clks IMX6SX_CLK_PLL1_SYS>;
153 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
172 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
178 clocks = <&clks IMX6SX_CLK_OCRAM>;
195 clocks = <&clks IMX6SX_CLK_GPU>,
196 <&clks IMX6SX_CLK_GPU>,
[all …]
Dimx25.dtsi97 clocks = <&clks 48>;
108 clocks = <&clks 48>;
118 clocks = <&clks 75>, <&clks 75>;
127 clocks = <&clks 76>, <&clks 76>;
136 clocks = <&clks 120>, <&clks 57>;
145 clocks = <&clks 121>, <&clks 57>;
155 clocks = <&clks 48>;
165 clocks = <&clks 51>;
176 clocks = <&clks 78>, <&clks 78>;
187 clocks = <&clks 102>;
[all …]
Dimx51.dtsi85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
[all …]
Dimx6ul.dtsi80 clocks = <&clks IMX6UL_CLK_ARM>,
81 <&clks IMX6UL_CLK_PLL2_BUS>,
82 <&clks IMX6UL_CLK_PLL2_PFD2>,
83 <&clks IMX6UL_CA7_SECONDARY_SEL>,
84 <&clks IMX6UL_CLK_STEP>,
85 <&clks IMX6UL_CLK_PLL1_SW>,
86 <&clks IMX6UL_CLK_PLL1_SYS>;
152 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
[all …]
Dimx53.dtsi64 clocks = <&clks IMX5_CLK_ARM>;
124 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
132 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
149 clocks = <&clks IMX5_CLK_SATA_GATE>,
150 <&clks IMX5_CLK_SATA_REF>,
151 <&clks IMX5_CLK_AHB>;
162 clocks = <&clks IMX5_CLK_IPU_GATE>,
163 <&clks IMX5_CLK_IPU_DI0_GATE>,
164 <&clks IMX5_CLK_IPU_DI1_GATE>;
230 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
[all …]
Dvfxxx.dtsi130 clocks = <&clks VF610_CLK_DMAMUX0>,
131 <&clks VF610_CLK_DMAMUX1>;
139 clocks = <&clks VF610_CLK_FLEXCAN0>,
140 <&clks VF610_CLK_FLEXCAN0>;
149 clocks = <&clks VF610_CLK_UART0>;
161 clocks = <&clks VF610_CLK_UART1>;
173 clocks = <&clks VF610_CLK_UART2>;
185 clocks = <&clks VF610_CLK_UART3>;
199 clocks = <&clks VF610_CLK_DSPI0>;
214 clocks = <&clks VF610_CLK_DSPI1>;
[all …]
Dimx6q.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
76 clocks = <&clks IMX6QDL_CLK_ARM>,
77 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
78 <&clks IMX6QDL_CLK_STEP>,
79 <&clks IMX6QDL_CLK_PLL1_SW>,
80 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
Dimx35.dtsi77 clocks = <&clks 51>;
88 clocks = <&clks 53>;
97 clocks = <&clks 9>, <&clks 70>;
106 clocks = <&clks 9>, <&clks 71>;
117 clocks = <&clks 52>;
128 clocks = <&clks 68>;
141 clocks = <&clks 35 &clks 35>;
151 clocks = <&clks 56>;
171 clocks = <&clks 9>, <&clks 72>;
183 clocks = <&clks 36 &clks 36>;
[all …]
/Linux-v4.19/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
71 clocks = <&clks MPC512x_CLK_NFC>;
138 clks: clock@f00 { label
163 clocks = <&clks MPC512x_CLK_BDLC>,
164 <&clks MPC512x_CLK_IPS>,
165 <&clks MPC512x_CLK_SYS>,
166 <&clks MPC512x_CLK_REF>,
167 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
/Linux-v4.19/drivers/clk/zynq/
Dclkc.c72 static struct clk *clks[clk_max]; variable
158 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
163 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
182 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
209 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
212 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
221 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
223 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
273 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
279 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
[all …]

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