1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2012 Sascha Hauer, Pengutronix 4 5#include "imx27-pinfunc.h" 6 7#include <dt-bindings/clock/imx27-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 /* 16 * The decompressor and also some bootloaders rely on a 17 * pre-existing /chosen node to be available to insert the 18 * command line and merge other ATAGS info. 19 * Also for U-Boot there must be a pre-existing /memory node. 20 */ 21 chosen {}; 22 memory { device_type = "memory"; }; 23 24 aliases { 25 ethernet0 = &fec; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 serial3 = &uart4; 38 serial4 = &uart5; 39 serial5 = &uart6; 40 spi0 = &cspi1; 41 spi1 = &cspi2; 42 spi2 = &cspi3; 43 }; 44 45 aitc: aitc-interrupt-controller@e0000000 { 46 compatible = "fsl,imx27-aitc", "fsl,avic"; 47 interrupt-controller; 48 #interrupt-cells = <1>; 49 reg = <0x10040000 0x1000>; 50 }; 51 52 clocks { 53 clk_osc26m: osc26m { 54 compatible = "fsl,imx-osc26m", "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <26000000>; 57 }; 58 }; 59 60 cpus { 61 #size-cells = <0>; 62 #address-cells = <1>; 63 64 cpu: cpu@0 { 65 device_type = "cpu"; 66 reg = <0>; 67 compatible = "arm,arm926ej-s"; 68 operating-points = < 69 /* kHz uV */ 70 266000 1300000 71 399000 1450000 72 >; 73 clock-latency = <62500>; 74 clocks = <&clks IMX27_CLK_CPU_DIV>; 75 voltage-tolerance = <5>; 76 }; 77 }; 78 79 soc { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 compatible = "simple-bus"; 83 interrupt-parent = <&aitc>; 84 ranges; 85 86 aipi@10000000 { /* AIPI1 */ 87 compatible = "fsl,aipi-bus", "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 reg = <0x10000000 0x20000>; 91 ranges; 92 93 dma: dma@10001000 { 94 compatible = "fsl,imx27-dma"; 95 reg = <0x10001000 0x1000>; 96 interrupts = <32>; 97 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, 98 <&clks IMX27_CLK_DMA_AHB_GATE>; 99 clock-names = "ipg", "ahb"; 100 #dma-cells = <1>; 101 #dma-channels = <16>; 102 }; 103 104 wdog: wdog@10002000 { 105 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 106 reg = <0x10002000 0x1000>; 107 interrupts = <27>; 108 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; 109 }; 110 111 gpt1: timer@10003000 { 112 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 113 reg = <0x10003000 0x1000>; 114 interrupts = <26>; 115 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, 116 <&clks IMX27_CLK_PER1_GATE>; 117 clock-names = "ipg", "per"; 118 }; 119 120 gpt2: timer@10004000 { 121 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 122 reg = <0x10004000 0x1000>; 123 interrupts = <25>; 124 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, 125 <&clks IMX27_CLK_PER1_GATE>; 126 clock-names = "ipg", "per"; 127 }; 128 129 gpt3: timer@10005000 { 130 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 131 reg = <0x10005000 0x1000>; 132 interrupts = <24>; 133 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, 134 <&clks IMX27_CLK_PER1_GATE>; 135 clock-names = "ipg", "per"; 136 }; 137 138 pwm: pwm@10006000 { 139 #pwm-cells = <2>; 140 compatible = "fsl,imx27-pwm"; 141 reg = <0x10006000 0x1000>; 142 interrupts = <23>; 143 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, 144 <&clks IMX27_CLK_PER1_GATE>; 145 clock-names = "ipg", "per"; 146 }; 147 148 rtc: rtc@10007000 { 149 compatible = "fsl,imx21-rtc"; 150 reg = <0x10007000 0x1000>; 151 interrupts = <22>; 152 clocks = <&clks IMX27_CLK_CKIL>, 153 <&clks IMX27_CLK_RTC_IPG_GATE>; 154 clock-names = "ref", "ipg"; 155 }; 156 157 kpp: kpp@10008000 { 158 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; 159 reg = <0x10008000 0x1000>; 160 interrupts = <21>; 161 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; 162 status = "disabled"; 163 }; 164 165 owire: owire@10009000 { 166 compatible = "fsl,imx27-owire", "fsl,imx21-owire"; 167 reg = <0x10009000 0x1000>; 168 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; 169 status = "disabled"; 170 }; 171 172 uart1: serial@1000a000 { 173 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 174 reg = <0x1000a000 0x1000>; 175 interrupts = <20>; 176 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, 177 <&clks IMX27_CLK_PER1_GATE>; 178 clock-names = "ipg", "per"; 179 status = "disabled"; 180 }; 181 182 uart2: serial@1000b000 { 183 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 184 reg = <0x1000b000 0x1000>; 185 interrupts = <19>; 186 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, 187 <&clks IMX27_CLK_PER1_GATE>; 188 clock-names = "ipg", "per"; 189 status = "disabled"; 190 }; 191 192 uart3: serial@1000c000 { 193 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 194 reg = <0x1000c000 0x1000>; 195 interrupts = <18>; 196 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, 197 <&clks IMX27_CLK_PER1_GATE>; 198 clock-names = "ipg", "per"; 199 status = "disabled"; 200 }; 201 202 uart4: serial@1000d000 { 203 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 204 reg = <0x1000d000 0x1000>; 205 interrupts = <17>; 206 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, 207 <&clks IMX27_CLK_PER1_GATE>; 208 clock-names = "ipg", "per"; 209 status = "disabled"; 210 }; 211 212 cspi1: cspi@1000e000 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "fsl,imx27-cspi"; 216 reg = <0x1000e000 0x1000>; 217 interrupts = <16>; 218 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, 219 <&clks IMX27_CLK_PER2_GATE>; 220 clock-names = "ipg", "per"; 221 status = "disabled"; 222 }; 223 224 cspi2: cspi@1000f000 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "fsl,imx27-cspi"; 228 reg = <0x1000f000 0x1000>; 229 interrupts = <15>; 230 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, 231 <&clks IMX27_CLK_PER2_GATE>; 232 clock-names = "ipg", "per"; 233 status = "disabled"; 234 }; 235 236 ssi1: ssi@10010000 { 237 #sound-dai-cells = <0>; 238 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; 239 reg = <0x10010000 0x1000>; 240 interrupts = <14>; 241 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; 242 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; 243 dma-names = "rx0", "tx0", "rx1", "tx1"; 244 fsl,fifo-depth = <8>; 245 status = "disabled"; 246 }; 247 248 ssi2: ssi@10011000 { 249 #sound-dai-cells = <0>; 250 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; 251 reg = <0x10011000 0x1000>; 252 interrupts = <13>; 253 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; 254 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; 255 dma-names = "rx0", "tx0", "rx1", "tx1"; 256 fsl,fifo-depth = <8>; 257 status = "disabled"; 258 }; 259 260 i2c1: i2c@10012000 { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 264 reg = <0x10012000 0x1000>; 265 interrupts = <12>; 266 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; 267 status = "disabled"; 268 }; 269 270 sdhci1: sdhci@10013000 { 271 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 272 reg = <0x10013000 0x1000>; 273 interrupts = <11>; 274 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, 275 <&clks IMX27_CLK_PER2_GATE>; 276 clock-names = "ipg", "per"; 277 dmas = <&dma 7>; 278 dma-names = "rx-tx"; 279 status = "disabled"; 280 }; 281 282 sdhci2: sdhci@10014000 { 283 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 284 reg = <0x10014000 0x1000>; 285 interrupts = <10>; 286 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, 287 <&clks IMX27_CLK_PER2_GATE>; 288 clock-names = "ipg", "per"; 289 dmas = <&dma 6>; 290 dma-names = "rx-tx"; 291 status = "disabled"; 292 }; 293 294 iomuxc: iomuxc@10015000 { 295 compatible = "fsl,imx27-iomuxc"; 296 reg = <0x10015000 0x600>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges; 300 301 gpio1: gpio@10015000 { 302 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 303 reg = <0x10015000 0x100>; 304 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 305 interrupts = <8>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 }; 311 312 gpio2: gpio@10015100 { 313 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 314 reg = <0x10015100 0x100>; 315 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 316 interrupts = <8>; 317 gpio-controller; 318 #gpio-cells = <2>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 323 gpio3: gpio@10015200 { 324 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 325 reg = <0x10015200 0x100>; 326 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 327 interrupts = <8>; 328 gpio-controller; 329 #gpio-cells = <2>; 330 interrupt-controller; 331 #interrupt-cells = <2>; 332 }; 333 334 gpio4: gpio@10015300 { 335 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 336 reg = <0x10015300 0x100>; 337 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 338 interrupts = <8>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 }; 344 345 gpio5: gpio@10015400 { 346 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 347 reg = <0x10015400 0x100>; 348 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 349 interrupts = <8>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 }; 355 356 gpio6: gpio@10015500 { 357 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 358 reg = <0x10015500 0x100>; 359 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; 360 interrupts = <8>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 }; 367 368 audmux: audmux@10016000 { 369 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; 370 reg = <0x10016000 0x1000>; 371 clocks = <&clks IMX27_CLK_DUMMY>; 372 clock-names = "audmux"; 373 status = "disabled"; 374 }; 375 376 cspi3: cspi@10017000 { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 compatible = "fsl,imx27-cspi"; 380 reg = <0x10017000 0x1000>; 381 interrupts = <6>; 382 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, 383 <&clks IMX27_CLK_PER2_GATE>; 384 clock-names = "ipg", "per"; 385 status = "disabled"; 386 }; 387 388 gpt4: timer@10019000 { 389 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 390 reg = <0x10019000 0x1000>; 391 interrupts = <4>; 392 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, 393 <&clks IMX27_CLK_PER1_GATE>; 394 clock-names = "ipg", "per"; 395 }; 396 397 gpt5: timer@1001a000 { 398 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 399 reg = <0x1001a000 0x1000>; 400 interrupts = <3>; 401 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, 402 <&clks IMX27_CLK_PER1_GATE>; 403 clock-names = "ipg", "per"; 404 }; 405 406 uart5: serial@1001b000 { 407 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 408 reg = <0x1001b000 0x1000>; 409 interrupts = <49>; 410 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, 411 <&clks IMX27_CLK_PER1_GATE>; 412 clock-names = "ipg", "per"; 413 status = "disabled"; 414 }; 415 416 uart6: serial@1001c000 { 417 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 418 reg = <0x1001c000 0x1000>; 419 interrupts = <48>; 420 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, 421 <&clks IMX27_CLK_PER1_GATE>; 422 clock-names = "ipg", "per"; 423 status = "disabled"; 424 }; 425 426 i2c2: i2c@1001d000 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 430 reg = <0x1001d000 0x1000>; 431 interrupts = <1>; 432 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; 433 status = "disabled"; 434 }; 435 436 sdhci3: sdhci@1001e000 { 437 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 438 reg = <0x1001e000 0x1000>; 439 interrupts = <9>; 440 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, 441 <&clks IMX27_CLK_PER2_GATE>; 442 clock-names = "ipg", "per"; 443 dmas = <&dma 36>; 444 dma-names = "rx-tx"; 445 status = "disabled"; 446 }; 447 448 gpt6: timer@1001f000 { 449 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; 450 reg = <0x1001f000 0x1000>; 451 interrupts = <2>; 452 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, 453 <&clks IMX27_CLK_PER1_GATE>; 454 clock-names = "ipg", "per"; 455 }; 456 }; 457 458 aipi@10020000 { /* AIPI2 */ 459 compatible = "fsl,aipi-bus", "simple-bus"; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 reg = <0x10020000 0x20000>; 463 ranges; 464 465 fb: fb@10021000 { 466 compatible = "fsl,imx27-fb", "fsl,imx21-fb"; 467 interrupts = <61>; 468 reg = <0x10021000 0x1000>; 469 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, 470 <&clks IMX27_CLK_LCDC_AHB_GATE>, 471 <&clks IMX27_CLK_PER3_GATE>; 472 clock-names = "ipg", "ahb", "per"; 473 status = "disabled"; 474 }; 475 476 coda: coda@10023000 { 477 compatible = "fsl,imx27-vpu", "cnm,codadx6"; 478 reg = <0x10023000 0x0200>; 479 interrupts = <53>; 480 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, 481 <&clks IMX27_CLK_VPU_AHB_GATE>; 482 clock-names = "per", "ahb"; 483 iram = <&iram>; 484 }; 485 486 usbotg: usb@10024000 { 487 compatible = "fsl,imx27-usb"; 488 reg = <0x10024000 0x200>; 489 interrupts = <56>; 490 clocks = <&clks IMX27_CLK_USB_IPG_GATE>, 491 <&clks IMX27_CLK_USB_AHB_GATE>, 492 <&clks IMX27_CLK_USB_DIV>; 493 clock-names = "ipg", "ahb", "per"; 494 fsl,usbmisc = <&usbmisc 0>; 495 status = "disabled"; 496 }; 497 498 usbh1: usb@10024200 { 499 compatible = "fsl,imx27-usb"; 500 reg = <0x10024200 0x200>; 501 interrupts = <54>; 502 clocks = <&clks IMX27_CLK_USB_IPG_GATE>, 503 <&clks IMX27_CLK_USB_AHB_GATE>, 504 <&clks IMX27_CLK_USB_DIV>; 505 clock-names = "ipg", "ahb", "per"; 506 fsl,usbmisc = <&usbmisc 1>; 507 dr_mode = "host"; 508 status = "disabled"; 509 }; 510 511 usbh2: usb@10024400 { 512 compatible = "fsl,imx27-usb"; 513 reg = <0x10024400 0x200>; 514 interrupts = <55>; 515 clocks = <&clks IMX27_CLK_USB_IPG_GATE>, 516 <&clks IMX27_CLK_USB_AHB_GATE>, 517 <&clks IMX27_CLK_USB_DIV>; 518 clock-names = "ipg", "ahb", "per"; 519 fsl,usbmisc = <&usbmisc 2>; 520 dr_mode = "host"; 521 status = "disabled"; 522 }; 523 524 usbmisc: usbmisc@10024600 { 525 #index-cells = <1>; 526 compatible = "fsl,imx27-usbmisc"; 527 reg = <0x10024600 0x200>; 528 }; 529 530 sahara2: sahara@10025000 { 531 compatible = "fsl,imx27-sahara"; 532 reg = <0x10025000 0x1000>; 533 interrupts = <59>; 534 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, 535 <&clks IMX27_CLK_SAHARA_AHB_GATE>; 536 clock-names = "ipg", "ahb"; 537 }; 538 539 clks: ccm@10027000{ 540 compatible = "fsl,imx27-ccm"; 541 reg = <0x10027000 0x1000>; 542 #clock-cells = <1>; 543 }; 544 545 iim: iim@10028000 { 546 compatible = "fsl,imx27-iim"; 547 reg = <0x10028000 0x1000>; 548 interrupts = <62>; 549 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; 550 }; 551 552 fec: ethernet@1002b000 { 553 compatible = "fsl,imx27-fec"; 554 reg = <0x1002b000 0x1000>; 555 interrupts = <50>; 556 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, 557 <&clks IMX27_CLK_FEC_AHB_GATE>; 558 clock-names = "ipg", "ahb"; 559 status = "disabled"; 560 }; 561 }; 562 563 nfc: nand@d8000000 { 564 #address-cells = <1>; 565 #size-cells = <1>; 566 compatible = "fsl,imx27-nand"; 567 reg = <0xd8000000 0x1000>; 568 interrupts = <29>; 569 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; 570 status = "disabled"; 571 }; 572 573 weim: weim@d8002000 { 574 #address-cells = <2>; 575 #size-cells = <1>; 576 compatible = "fsl,imx27-weim"; 577 reg = <0xd8002000 0x1000>; 578 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; 579 ranges = < 580 0 0 0xc0000000 0x08000000 581 1 0 0xc8000000 0x08000000 582 2 0 0xd0000000 0x02000000 583 3 0 0xd2000000 0x02000000 584 4 0 0xd4000000 0x02000000 585 5 0 0xd6000000 0x02000000 586 >; 587 status = "disabled"; 588 }; 589 590 iram: iram@ffff4c00 { 591 compatible = "mmio-sram"; 592 reg = <0xffff4c00 0xb400>; 593 }; 594 }; 595}; 596
