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Searched refs:clkctrl_offs (Results 1 – 13 of 13) sorted by relevance

/Linux-v4.19/arch/arm/mach-omap2/
Domap_hwmod_7xx_data.c62 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
83 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
97 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
110 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
132 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
145 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
158 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
171 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
184 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
207 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
[all …]
Domap_hwmod_54xx_data.c61 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
82 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
96 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
109 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
122 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
144 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
157 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
170 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
183 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
236 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
[all …]
Domap_hwmod_43xx_data.c33 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
47 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
66 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
84 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
102 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
131 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
144 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
157 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
170 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
183 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
[all …]
Dcm33xx.c94 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
96 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); in _clkctrl_idlest()
110 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
114 v = _clkctrl_idlest(inst, clkctrl_offs); in _is_module_ready()
229 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_ready() argument
234 omap_test_timeout(_is_module_ready(inst, clkctrl_offs), in am33xx_cm_wait_module_ready()
252 static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_idle() argument
257 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) == in am33xx_cm_wait_module_idle()
274 u16 clkctrl_offs) in am33xx_cm_module_enable() argument
278 v = am33xx_cm_read_reg(inst, clkctrl_offs); in am33xx_cm_module_enable()
[all …]
Domap_hwmod_44xx_data.c64 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
85 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
99 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
112 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
125 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
147 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
162 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
175 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
188 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
229 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
[all …]
Domap_hwmod_81xx_data.c185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
254 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
291 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
312 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
333 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
371 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
408 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
428 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
501 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
[all …]
Dcm.h64 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
65 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
66 u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
75 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
76 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
77 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
Domap_hwmod_33xx_data.c43 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
58 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
78 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
113 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
146 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
166 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
184 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
211 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
227 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
246 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
[all …]
Dcminst44xx.c88 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
90 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in _clkctrl_idlest()
105 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
109 v = _clkctrl_idlest(part, inst, clkctrl_offs); in _is_module_ready()
277 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_ready() argument
282 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), in omap4_cminst_wait_module_ready()
300 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_idle() argument
305 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == in omap4_cminst_wait_module_idle()
322 u16 clkctrl_offs) in omap4_cminst_module_enable() argument
326 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in omap4_cminst_module_enable()
[all …]
Dcm_common.c147 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_enable() argument
155 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs); in omap_cm_module_enable()
169 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_disable() argument
177 cm_ll_data->module_disable(part, inst, clkctrl_offs); in omap_cm_module_disable()
181 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_xlate_clkctrl() argument
188 return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); in omap_cm_xlate_clkctrl()
Domap_hwmod.c771 oh->prcm.omap4.clkctrl_offs); in _omap4_xlate_clkctrl()
1016 if (oh->prcm.omap4.clkctrl_offs) in _omap4_has_clkctrl_clock()
1019 if (!oh->prcm.omap4.clkctrl_offs && in _omap4_has_clkctrl_clock()
1072 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); in _omap4_enable_module()
1103 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_disable()
1662 oh->prcm.omap4.clkctrl_offs); in _omap4_disable_module()
2742 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_ready()
Domap_hwmod.h381 u16 clkctrl_offs; member
Domap_hwmod_33xx_43xx_ipblock_data.c29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))