1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_data/i2c-omap.h>
18
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
21
22 #include "control.h"
23 #include "cm33xx.h"
24 #include "prm33xx.h"
25 #include "prm-regbits-33xx.h"
26 #include "i2c.h"
27 #include "wd_timer.h"
28 #include "omap_hwmod_33xx_43xx_common_data.h"
29
30 /*
31 * IP blocks
32 */
33
34 /* emif */
35 static struct omap_hwmod am33xx_emif_hwmod = {
36 .name = "emif",
37 .class = &am33xx_emif_hwmod_class,
38 .clkdm_name = "l3_clkdm",
39 .flags = HWMOD_INIT_NO_IDLE,
40 .main_clk = "dpll_ddr_m2_div2_ck",
41 .prcm = {
42 .omap4 = {
43 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
44 .modulemode = MODULEMODE_SWCTRL,
45 },
46 },
47 };
48
49 /* l4_hs */
50 static struct omap_hwmod am33xx_l4_hs_hwmod = {
51 .name = "l4_hs",
52 .class = &am33xx_l4_hwmod_class,
53 .clkdm_name = "l4hs_clkdm",
54 .flags = HWMOD_INIT_NO_IDLE,
55 .main_clk = "l4hs_gclk",
56 .prcm = {
57 .omap4 = {
58 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
59 .modulemode = MODULEMODE_SWCTRL,
60 },
61 },
62 };
63
64 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
65 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
66 };
67
68 /* wkup_m3 */
69 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
70 .name = "wkup_m3",
71 .class = &am33xx_wkup_m3_hwmod_class,
72 .clkdm_name = "l4_wkup_aon_clkdm",
73 /* Keep hardreset asserted */
74 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
75 .main_clk = "dpll_core_m4_div2_ck",
76 .prcm = {
77 .omap4 = {
78 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
79 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
80 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
81 .modulemode = MODULEMODE_SWCTRL,
82 },
83 },
84 .rst_lines = am33xx_wkup_m3_resets,
85 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
86 };
87
88 /*
89 * 'adc/tsc' class
90 * TouchScreen Controller (Anolog-To-Digital Converter)
91 */
92 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
93 .rev_offs = 0x00,
94 .sysc_offs = 0x10,
95 .sysc_flags = SYSC_HAS_SIDLEMODE,
96 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
97 SIDLE_SMART_WKUP),
98 .sysc_fields = &omap_hwmod_sysc_type2,
99 };
100
101 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
102 .name = "adc_tsc",
103 .sysc = &am33xx_adc_tsc_sysc,
104 };
105
106 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
107 .name = "adc_tsc",
108 .class = &am33xx_adc_tsc_hwmod_class,
109 .clkdm_name = "l4_wkup_clkdm",
110 .main_clk = "adc_tsc_fck",
111 .prcm = {
112 .omap4 = {
113 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
114 .modulemode = MODULEMODE_SWCTRL,
115 },
116 },
117 };
118
119 /*
120 * Modules omap_hwmod structures
121 *
122 * The following IPs are excluded for the moment because:
123 * - They do not need an explicit SW control using omap_hwmod API.
124 * - They still need to be validated with the driver
125 * properly adapted to omap_hwmod / omap_device
126 *
127 * - cEFUSE (doesn't fall under any ocp_if)
128 * - clkdiv32k
129 * - ocp watch point
130 */
131 #if 0
132 /*
133 * 'cefuse' class
134 */
135 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
136 .name = "cefuse",
137 };
138
139 static struct omap_hwmod am33xx_cefuse_hwmod = {
140 .name = "cefuse",
141 .class = &am33xx_cefuse_hwmod_class,
142 .clkdm_name = "l4_cefuse_clkdm",
143 .main_clk = "cefuse_fck",
144 .prcm = {
145 .omap4 = {
146 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
147 .modulemode = MODULEMODE_SWCTRL,
148 },
149 },
150 };
151
152 /*
153 * 'clkdiv32k' class
154 */
155 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
156 .name = "clkdiv32k",
157 };
158
159 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
160 .name = "clkdiv32k",
161 .class = &am33xx_clkdiv32k_hwmod_class,
162 .clkdm_name = "clk_24mhz_clkdm",
163 .main_clk = "clkdiv32k_ick",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
167 .modulemode = MODULEMODE_SWCTRL,
168 },
169 },
170 };
171
172 /* ocpwp */
173 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
174 .name = "ocpwp",
175 };
176
177 static struct omap_hwmod am33xx_ocpwp_hwmod = {
178 .name = "ocpwp",
179 .class = &am33xx_ocpwp_hwmod_class,
180 .clkdm_name = "l4ls_clkdm",
181 .main_clk = "l4ls_gclk",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
185 .modulemode = MODULEMODE_SWCTRL,
186 },
187 },
188 };
189 #endif
190
191 /*
192 * 'debugss' class
193 * debug sub system
194 */
195 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
196 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
197 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
198 };
199
200 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
201 .name = "debugss",
202 };
203
204 static struct omap_hwmod am33xx_debugss_hwmod = {
205 .name = "debugss",
206 .class = &am33xx_debugss_hwmod_class,
207 .clkdm_name = "l3_aon_clkdm",
208 .main_clk = "trace_clk_div_ck",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
212 .modulemode = MODULEMODE_SWCTRL,
213 },
214 },
215 .opt_clks = debugss_opt_clks,
216 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
217 };
218
219 static struct omap_hwmod am33xx_control_hwmod = {
220 .name = "control",
221 .class = &am33xx_control_hwmod_class,
222 .clkdm_name = "l4_wkup_clkdm",
223 .flags = HWMOD_INIT_NO_IDLE,
224 .main_clk = "dpll_core_m4_div2_ck",
225 .prcm = {
226 .omap4 = {
227 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
228 .modulemode = MODULEMODE_SWCTRL,
229 },
230 },
231 };
232
233 /* gpio0 */
234 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
235 { .role = "dbclk", .clk = "gpio0_dbclk" },
236 };
237
238 static struct omap_hwmod am33xx_gpio0_hwmod = {
239 .name = "gpio1",
240 .class = &am33xx_gpio_hwmod_class,
241 .clkdm_name = "l4_wkup_clkdm",
242 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
243 .main_clk = "dpll_core_m4_div2_ck",
244 .prcm = {
245 .omap4 = {
246 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
247 .modulemode = MODULEMODE_SWCTRL,
248 },
249 },
250 .opt_clks = gpio0_opt_clks,
251 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
252 };
253
254 /* lcdc */
255 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
256 .rev_offs = 0x0,
257 .sysc_offs = 0x54,
258 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
260 .sysc_fields = &omap_hwmod_sysc_type2,
261 };
262
263 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
264 .name = "lcdc",
265 .sysc = &lcdc_sysc,
266 };
267
268 static struct omap_hwmod am33xx_lcdc_hwmod = {
269 .name = "lcdc",
270 .class = &am33xx_lcdc_hwmod_class,
271 .clkdm_name = "lcdc_clkdm",
272 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
273 .main_clk = "lcd_gclk",
274 .prcm = {
275 .omap4 = {
276 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
277 .modulemode = MODULEMODE_SWCTRL,
278 },
279 },
280 };
281
282 /*
283 * 'usb_otg' class
284 * high-speed on-the-go universal serial bus (usb_otg) controller
285 */
286 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
287 .rev_offs = 0x0,
288 .sysc_offs = 0x10,
289 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
290 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
291 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
292 .sysc_fields = &omap_hwmod_sysc_type2,
293 };
294
295 static struct omap_hwmod_class am33xx_usbotg_class = {
296 .name = "usbotg",
297 .sysc = &am33xx_usbhsotg_sysc,
298 };
299
300 static struct omap_hwmod am33xx_usbss_hwmod = {
301 .name = "usb_otg_hs",
302 .class = &am33xx_usbotg_class,
303 .clkdm_name = "l3s_clkdm",
304 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
305 .main_clk = "usbotg_fck",
306 .prcm = {
307 .omap4 = {
308 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312 };
313
314
315 /*
316 * Interfaces
317 */
318
319 /* l3 main -> emif */
320 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
321 .master = &am33xx_l3_main_hwmod,
322 .slave = &am33xx_emif_hwmod,
323 .clk = "dpll_core_m4_ck",
324 .user = OCP_USER_MPU | OCP_USER_SDMA,
325 };
326
327 /* l3 main -> l4 hs */
328 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
329 .master = &am33xx_l3_main_hwmod,
330 .slave = &am33xx_l4_hs_hwmod,
331 .clk = "l3s_gclk",
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333 };
334
335 /* wkup m3 -> l4 wkup */
336 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
337 .master = &am33xx_wkup_m3_hwmod,
338 .slave = &am33xx_l4_wkup_hwmod,
339 .clk = "dpll_core_m4_div2_ck",
340 .user = OCP_USER_MPU | OCP_USER_SDMA,
341 };
342
343 /* l4 wkup -> wkup m3 */
344 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
345 .master = &am33xx_l4_wkup_hwmod,
346 .slave = &am33xx_wkup_m3_hwmod,
347 .clk = "dpll_core_m4_div2_ck",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349 };
350
351 /* l4 hs -> pru-icss */
352 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
353 .master = &am33xx_l4_hs_hwmod,
354 .slave = &am33xx_pruss_hwmod,
355 .clk = "dpll_core_m4_ck",
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357 };
358
359 /* l3_main -> debugss */
360 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
361 .master = &am33xx_l3_main_hwmod,
362 .slave = &am33xx_debugss_hwmod,
363 .clk = "dpll_core_m4_ck",
364 .user = OCP_USER_MPU,
365 };
366
367 /* l4 wkup -> smartreflex0 */
368 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
369 .master = &am33xx_l4_wkup_hwmod,
370 .slave = &am33xx_smartreflex0_hwmod,
371 .clk = "dpll_core_m4_div2_ck",
372 .user = OCP_USER_MPU,
373 };
374
375 /* l4 wkup -> smartreflex1 */
376 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
377 .master = &am33xx_l4_wkup_hwmod,
378 .slave = &am33xx_smartreflex1_hwmod,
379 .clk = "dpll_core_m4_div2_ck",
380 .user = OCP_USER_MPU,
381 };
382
383 /* l4 wkup -> control */
384 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
385 .master = &am33xx_l4_wkup_hwmod,
386 .slave = &am33xx_control_hwmod,
387 .clk = "dpll_core_m4_div2_ck",
388 .user = OCP_USER_MPU,
389 };
390
391 /* L4 WKUP -> I2C1 */
392 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
393 .master = &am33xx_l4_wkup_hwmod,
394 .slave = &am33xx_i2c1_hwmod,
395 .clk = "dpll_core_m4_div2_ck",
396 .user = OCP_USER_MPU,
397 };
398
399 /* L4 WKUP -> GPIO1 */
400 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
401 .master = &am33xx_l4_wkup_hwmod,
402 .slave = &am33xx_gpio0_hwmod,
403 .clk = "dpll_core_m4_div2_ck",
404 .user = OCP_USER_MPU | OCP_USER_SDMA,
405 };
406
407 /* L4 WKUP -> ADC_TSC */
408 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
409 .master = &am33xx_l4_wkup_hwmod,
410 .slave = &am33xx_adc_tsc_hwmod,
411 .clk = "dpll_core_m4_div2_ck",
412 .user = OCP_USER_MPU,
413 };
414
415 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
416 .master = &am33xx_l4_hs_hwmod,
417 .slave = &am33xx_cpgmac0_hwmod,
418 .clk = "cpsw_125mhz_gclk",
419 .user = OCP_USER_MPU,
420 };
421
422 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
423 .master = &am33xx_l3_main_hwmod,
424 .slave = &am33xx_lcdc_hwmod,
425 .clk = "dpll_core_m4_ck",
426 .user = OCP_USER_MPU,
427 };
428
429 /* l4 wkup -> timer1 */
430 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
431 .master = &am33xx_l4_wkup_hwmod,
432 .slave = &am33xx_timer1_hwmod,
433 .clk = "dpll_core_m4_div2_ck",
434 .user = OCP_USER_MPU,
435 };
436
437 /* l4 wkup -> uart1 */
438 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
439 .master = &am33xx_l4_wkup_hwmod,
440 .slave = &am33xx_uart1_hwmod,
441 .clk = "dpll_core_m4_div2_ck",
442 .user = OCP_USER_MPU,
443 };
444
445 /* l4 wkup -> wd_timer1 */
446 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
447 .master = &am33xx_l4_wkup_hwmod,
448 .slave = &am33xx_wd_timer1_hwmod,
449 .clk = "dpll_core_m4_div2_ck",
450 .user = OCP_USER_MPU,
451 };
452
453 /* usbss */
454 /* l3 s -> USBSS interface */
455 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
456 .master = &am33xx_l3_s_hwmod,
457 .slave = &am33xx_usbss_hwmod,
458 .clk = "l3s_gclk",
459 .user = OCP_USER_MPU,
460 .flags = OCPIF_SWSUP_IDLE,
461 };
462
463 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
464 &am33xx_l3_main__emif,
465 &am33xx_mpu__l3_main,
466 &am33xx_mpu__prcm,
467 &am33xx_l3_s__l4_ls,
468 &am33xx_l3_s__l4_wkup,
469 &am33xx_l3_main__l4_hs,
470 &am33xx_l3_main__l3_s,
471 &am33xx_l3_main__l3_instr,
472 &am33xx_l3_main__gfx,
473 &am33xx_l3_s__l3_main,
474 &am33xx_pruss__l3_main,
475 &am33xx_wkup_m3__l4_wkup,
476 &am33xx_gfx__l3_main,
477 &am33xx_l3_main__debugss,
478 &am33xx_l4_wkup__wkup_m3,
479 &am33xx_l4_wkup__control,
480 &am33xx_l4_wkup__smartreflex0,
481 &am33xx_l4_wkup__smartreflex1,
482 &am33xx_l4_wkup__uart1,
483 &am33xx_l4_wkup__timer1,
484 &am33xx_l4_wkup__rtc,
485 &am33xx_l4_wkup__i2c1,
486 &am33xx_l4_wkup__gpio0,
487 &am33xx_l4_wkup__adc_tsc,
488 &am33xx_l4_wkup__wd_timer1,
489 &am33xx_l4_hs__pruss,
490 &am33xx_l4_per__dcan0,
491 &am33xx_l4_per__dcan1,
492 &am33xx_l4_per__gpio1,
493 &am33xx_l4_per__gpio2,
494 &am33xx_l4_per__gpio3,
495 &am33xx_l4_per__i2c2,
496 &am33xx_l4_per__i2c3,
497 &am33xx_l4_per__mailbox,
498 &am33xx_l4_ls__mcasp0,
499 &am33xx_l4_ls__mcasp1,
500 &am33xx_l4_ls__mmc0,
501 &am33xx_l4_ls__mmc1,
502 &am33xx_l3_s__mmc2,
503 &am33xx_l4_ls__timer2,
504 &am33xx_l4_ls__timer3,
505 &am33xx_l4_ls__timer4,
506 &am33xx_l4_ls__timer5,
507 &am33xx_l4_ls__timer6,
508 &am33xx_l4_ls__timer7,
509 &am33xx_l3_main__tpcc,
510 &am33xx_l4_ls__uart2,
511 &am33xx_l4_ls__uart3,
512 &am33xx_l4_ls__uart4,
513 &am33xx_l4_ls__uart5,
514 &am33xx_l4_ls__uart6,
515 &am33xx_l4_ls__spinlock,
516 &am33xx_l4_ls__elm,
517 &am33xx_l4_ls__epwmss0,
518 &am33xx_l4_ls__epwmss1,
519 &am33xx_l4_ls__epwmss2,
520 &am33xx_l3_s__gpmc,
521 &am33xx_l3_main__lcdc,
522 &am33xx_l4_ls__mcspi0,
523 &am33xx_l4_ls__mcspi1,
524 &am33xx_l3_main__tptc0,
525 &am33xx_l3_main__tptc1,
526 &am33xx_l3_main__tptc2,
527 &am33xx_l3_main__ocmc,
528 &am33xx_l3_s__usbss,
529 &am33xx_l4_hs__cpgmac0,
530 &am33xx_cpgmac0__mdio,
531 &am33xx_l3_main__sha0,
532 &am33xx_l3_main__aes0,
533 &am33xx_l4_per__rng,
534 NULL,
535 };
536
am33xx_hwmod_init(void)537 int __init am33xx_hwmod_init(void)
538 {
539 omap_hwmod_am33xx_reg();
540 omap_hwmod_init();
541 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
542 }
543
