Searched refs:__REG (Results 1 – 13 of 13) sorted by relevance
9 #define UDCCR __REG(0x40600000) /* UDC Control Register */33 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */34 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */48 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */49 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */57 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */58 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */85 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */86 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */104 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */[all …]
11 #define RCNR __REG(0x40900000) /* RTC Count Register */12 #define RTAR __REG(0x40900004) /* RTC Alarm Register */13 #define RTSR __REG(0x40900008) /* RTC Status Register */14 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */15 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
11 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */[all …]
23 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */24 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */25 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */26 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */27 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */28 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */29 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */30 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */31 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */32 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */[all …]
29 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */30 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */31 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */32 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */33 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */34 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */35 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */36 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */37 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */38 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))[all …]
11 #define POCR __REG(0x40500000) /* PCM Out Control Register */15 #define PICR __REG(0x40500004) /* PCM In Control Register */19 #define MCCR __REG(0x40500008) /* Mic In Control Register */23 #define GCR __REG(0x4050000C) /* Global Control Register */39 #define POSR __REG(0x40500010) /* PCM Out Status Register */43 #define PISR __REG(0x40500014) /* PCM In Status Register */48 #define MCSR __REG(0x40500018) /* Mic In Status Register */53 #define GSR __REG(0x4050001C) /* Global Status Register */72 #define CAR __REG(0x40500020) /* CODEC Access Register */75 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */[all …]
43 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) macro48 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))54 # define __REG(x) io_p2v(x) macro
111 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */112 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */113 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */114 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */120 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */[all …]
44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) macro49 # define __REG(x) io_p2v(x) macro
36 #define SACR0 __REG(0x40400000) /* Global Control Register */37 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */38 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Reg…39 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */40 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */41 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */42 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
15 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ macro
116 __REG ## list (cc, abi, type, name, size, align)
