1 /*
2 * pxa2xx-i2s.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * lrg@slimlogic.co.uk
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/initval.h>
24 #include <sound/soc.h>
25 #include <sound/pxa2xx-lib.h>
26 #include <sound/dmaengine_pcm.h>
27
28 #include <mach/hardware.h>
29 #include <mach/audio.h>
30
31 #include "pxa2xx-i2s.h"
32
33 /*
34 * I2S Controller Register and Bit Definitions
35 */
36 #define SACR0 __REG(0x40400000) /* Global Control Register */
37 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
38 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
39 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
40 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
41 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
42 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
43
44 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
45 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
46 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
47 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
48 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
49 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
50 #define SACR0_ENB (1 << 0) /* Enable I2S Link */
51 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
52 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
53 #define SACR1_DREC (1 << 3) /* Disable Recording Function */
54 #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
55
56 #define SASR0_I2SOFF (1 << 7) /* Controller Status */
57 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
58 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
59 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
60 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
61 #define SASR0_BSY (1 << 2) /* I2S Busy */
62 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
63 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
64
65 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
66 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
67
68 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
69 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
70 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
71 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
72
73 struct pxa_i2s_port {
74 u32 sadiv;
75 u32 sacr0;
76 u32 sacr1;
77 u32 saimr;
78 int master;
79 u32 fmt;
80 };
81 static struct pxa_i2s_port pxa_i2s;
82 static struct clk *clk_i2s;
83 static int clk_ena = 0;
84
85 static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
86 .addr = __PREG(SADR),
87 .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
88 .chan_name = "tx",
89 .maxburst = 32,
90 };
91
92 static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
93 .addr = __PREG(SADR),
94 .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
95 .chan_name = "rx",
96 .maxburst = 32,
97 };
98
pxa2xx_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)99 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
100 struct snd_soc_dai *dai)
101 {
102 struct snd_soc_pcm_runtime *rtd = substream->private_data;
103 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
104
105 if (IS_ERR(clk_i2s))
106 return PTR_ERR(clk_i2s);
107
108 if (!cpu_dai->active)
109 SACR0 = 0;
110
111 return 0;
112 }
113
114 /* wait for I2S controller to be ready */
pxa_i2s_wait(void)115 static int pxa_i2s_wait(void)
116 {
117 int i;
118
119 /* flush the Rx FIFO */
120 for (i = 0; i < 16; i++)
121 SADR;
122 return 0;
123 }
124
pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)125 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
126 unsigned int fmt)
127 {
128 /* interface format */
129 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
130 case SND_SOC_DAIFMT_I2S:
131 pxa_i2s.fmt = 0;
132 break;
133 case SND_SOC_DAIFMT_LEFT_J:
134 pxa_i2s.fmt = SACR1_AMSL;
135 break;
136 }
137
138 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
139 case SND_SOC_DAIFMT_CBS_CFS:
140 pxa_i2s.master = 1;
141 break;
142 case SND_SOC_DAIFMT_CBM_CFS:
143 pxa_i2s.master = 0;
144 break;
145 default:
146 break;
147 }
148 return 0;
149 }
150
pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)151 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
152 int clk_id, unsigned int freq, int dir)
153 {
154 if (clk_id != PXA2XX_I2S_SYSCLK)
155 return -ENODEV;
156
157 return 0;
158 }
159
pxa2xx_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)160 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
161 struct snd_pcm_hw_params *params,
162 struct snd_soc_dai *dai)
163 {
164 struct snd_dmaengine_dai_dma_data *dma_data;
165
166 if (WARN_ON(IS_ERR(clk_i2s)))
167 return -EINVAL;
168 clk_prepare_enable(clk_i2s);
169 clk_ena = 1;
170 pxa_i2s_wait();
171
172 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
173 dma_data = &pxa2xx_i2s_pcm_stereo_out;
174 else
175 dma_data = &pxa2xx_i2s_pcm_stereo_in;
176
177 snd_soc_dai_set_dma_data(dai, substream, dma_data);
178
179 /* is port used by another stream */
180 if (!(SACR0 & SACR0_ENB)) {
181 SACR0 = 0;
182 if (pxa_i2s.master)
183 SACR0 |= SACR0_BCKD;
184
185 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
186 SACR1 |= pxa_i2s.fmt;
187 }
188 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
189 SAIMR |= SAIMR_TFS;
190 else
191 SAIMR |= SAIMR_RFS;
192
193 switch (params_rate(params)) {
194 case 8000:
195 SADIV = 0x48;
196 break;
197 case 11025:
198 SADIV = 0x34;
199 break;
200 case 16000:
201 SADIV = 0x24;
202 break;
203 case 22050:
204 SADIV = 0x1a;
205 break;
206 case 44100:
207 SADIV = 0xd;
208 break;
209 case 48000:
210 SADIV = 0xc;
211 break;
212 case 96000: /* not in manual and possibly slightly inaccurate */
213 SADIV = 0x6;
214 break;
215 }
216
217 return 0;
218 }
219
pxa2xx_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)220 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
221 struct snd_soc_dai *dai)
222 {
223 int ret = 0;
224
225 switch (cmd) {
226 case SNDRV_PCM_TRIGGER_START:
227 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
228 SACR1 &= ~SACR1_DRPL;
229 else
230 SACR1 &= ~SACR1_DREC;
231 SACR0 |= SACR0_ENB;
232 break;
233 case SNDRV_PCM_TRIGGER_RESUME:
234 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
235 case SNDRV_PCM_TRIGGER_STOP:
236 case SNDRV_PCM_TRIGGER_SUSPEND:
237 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
238 break;
239 default:
240 ret = -EINVAL;
241 }
242
243 return ret;
244 }
245
pxa2xx_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)246 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
247 struct snd_soc_dai *dai)
248 {
249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
250 SACR1 |= SACR1_DRPL;
251 SAIMR &= ~SAIMR_TFS;
252 } else {
253 SACR1 |= SACR1_DREC;
254 SAIMR &= ~SAIMR_RFS;
255 }
256
257 if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
258 SACR0 &= ~SACR0_ENB;
259 pxa_i2s_wait();
260 if (clk_ena) {
261 clk_disable_unprepare(clk_i2s);
262 clk_ena = 0;
263 }
264 }
265 }
266
267 #ifdef CONFIG_PM
pxa2xx_i2s_suspend(struct snd_soc_dai * dai)268 static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
269 {
270 /* store registers */
271 pxa_i2s.sacr0 = SACR0;
272 pxa_i2s.sacr1 = SACR1;
273 pxa_i2s.saimr = SAIMR;
274 pxa_i2s.sadiv = SADIV;
275
276 /* deactivate link */
277 SACR0 &= ~SACR0_ENB;
278 pxa_i2s_wait();
279 return 0;
280 }
281
pxa2xx_i2s_resume(struct snd_soc_dai * dai)282 static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
283 {
284 pxa_i2s_wait();
285
286 SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
287 SACR1 = pxa_i2s.sacr1;
288 SAIMR = pxa_i2s.saimr;
289 SADIV = pxa_i2s.sadiv;
290
291 SACR0 = pxa_i2s.sacr0;
292
293 return 0;
294 }
295
296 #else
297 #define pxa2xx_i2s_suspend NULL
298 #define pxa2xx_i2s_resume NULL
299 #endif
300
pxa2xx_i2s_probe(struct snd_soc_dai * dai)301 static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
302 {
303 clk_i2s = clk_get(dai->dev, "I2SCLK");
304 if (IS_ERR(clk_i2s))
305 return PTR_ERR(clk_i2s);
306
307 /*
308 * PXA Developer's Manual:
309 * If SACR0[ENB] is toggled in the middle of a normal operation,
310 * the SACR0[RST] bit must also be set and cleared to reset all
311 * I2S controller registers.
312 */
313 SACR0 = SACR0_RST;
314 SACR0 = 0;
315 /* Make sure RPL and REC are disabled */
316 SACR1 = SACR1_DRPL | SACR1_DREC;
317 /* Along with FIFO servicing */
318 SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
319
320 snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
321 &pxa2xx_i2s_pcm_stereo_in);
322
323 return 0;
324 }
325
pxa2xx_i2s_remove(struct snd_soc_dai * dai)326 static int pxa2xx_i2s_remove(struct snd_soc_dai *dai)
327 {
328 clk_put(clk_i2s);
329 clk_i2s = ERR_PTR(-ENOENT);
330 return 0;
331 }
332
333 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
334 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
335 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
336
337 static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
338 .startup = pxa2xx_i2s_startup,
339 .shutdown = pxa2xx_i2s_shutdown,
340 .trigger = pxa2xx_i2s_trigger,
341 .hw_params = pxa2xx_i2s_hw_params,
342 .set_fmt = pxa2xx_i2s_set_dai_fmt,
343 .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
344 };
345
346 static struct snd_soc_dai_driver pxa_i2s_dai = {
347 .probe = pxa2xx_i2s_probe,
348 .remove = pxa2xx_i2s_remove,
349 .suspend = pxa2xx_i2s_suspend,
350 .resume = pxa2xx_i2s_resume,
351 .playback = {
352 .channels_min = 2,
353 .channels_max = 2,
354 .rates = PXA2XX_I2S_RATES,
355 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
356 .capture = {
357 .channels_min = 2,
358 .channels_max = 2,
359 .rates = PXA2XX_I2S_RATES,
360 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
361 .ops = &pxa_i2s_dai_ops,
362 .symmetric_rates = 1,
363 };
364
365 static const struct snd_soc_component_driver pxa_i2s_component = {
366 .name = "pxa-i2s",
367 .ops = &pxa2xx_pcm_ops,
368 .pcm_new = pxa2xx_soc_pcm_new,
369 .pcm_free = pxa2xx_pcm_free_dma_buffers,
370 };
371
pxa2xx_i2s_drv_probe(struct platform_device * pdev)372 static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
373 {
374 return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
375 &pxa_i2s_dai, 1);
376 }
377
378 static struct platform_driver pxa2xx_i2s_driver = {
379 .probe = pxa2xx_i2s_drv_probe,
380
381 .driver = {
382 .name = "pxa2xx-i2s",
383 },
384 };
385
pxa2xx_i2s_init(void)386 static int __init pxa2xx_i2s_init(void)
387 {
388 clk_i2s = ERR_PTR(-ENOENT);
389 return platform_driver_register(&pxa2xx_i2s_driver);
390 }
391
pxa2xx_i2s_exit(void)392 static void __exit pxa2xx_i2s_exit(void)
393 {
394 platform_driver_unregister(&pxa2xx_i2s_driver);
395 }
396
397 module_init(pxa2xx_i2s_init);
398 module_exit(pxa2xx_i2s_exit);
399
400 /* Module information */
401 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
402 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
403 MODULE_LICENSE("GPL");
404 MODULE_ALIAS("platform:pxa2xx-i2s");
405
