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Searched refs:V3D_WRITE (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/vc4/
Dvc4_irq.c96 V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size); in vc4_overflow_mem_work()
97 V3D_WRITE(V3D_BPOS, bo->base.base.size); in vc4_overflow_mem_work()
98 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
99 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
201 V3D_WRITE(V3D_INTCTL, intctl); in vc4_irq()
205 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM); in vc4_irq()
238 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_preinstall()
247 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS); in vc4_irq_postinstall()
258 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS); in vc4_irq_uninstall()
261 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_uninstall()
[all …]
Dvc4_perfmon.c39 V3D_WRITE(V3D_PCTRS(i), perfmon->events[i]); in vc4_perfmon_start()
42 V3D_WRITE(V3D_PCTRC, mask); in vc4_perfmon_start()
43 V3D_WRITE(V3D_PCTRE, V3D_PCTRE_EN | mask); in vc4_perfmon_start()
61 V3D_WRITE(V3D_PCTRE, 0); in vc4_perfmon_stop()
Dvc4_v3d.c157 V3D_WRITE(V3D_VPMBASE, 0); in vc4_v3d_init_hw()
396 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_bind()
397 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_bind()
429 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_unbind()
430 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_unbind()
Dvc4_gem.c369 V3D_WRITE(V3D_CTNCA(thread), start); in submit_cl()
370 V3D_WRITE(V3D_CTNEA(thread), end); in submit_cl()
430 V3D_WRITE(V3D_L2CACTL, in vc4_flush_caches()
433 V3D_WRITE(V3D_SLCACTL, in vc4_flush_caches()
445 V3D_WRITE(V3D_L2CACTL, in vc4_flush_texture_caches()
448 V3D_WRITE(V3D_SLCACTL, in vc4_flush_texture_caches()
Dvc4_drv.h436 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) macro
/Linux-v4.19/drivers/gpu/drm/v3d/
Dv3d_mmu.c45 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) | in v3d_mmu_flush_all()
48 V3D_WRITE(V3D_MMUC_CONTROL, in v3d_mmu_flush_all()
69 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); in v3d_mmu_set_page_table()
70 V3D_WRITE(V3D_MMU_CTL, in v3d_mmu_set_page_table()
76 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR, in v3d_mmu_set_page_table()
79 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE); in v3d_mmu_set_page_table()
Dv3d_irq.c118 V3D_WRITE(V3D_HUB_INT_CLR, intsts); in v3d_hub_irq()
152 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); in v3d_irq_init()
177 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); in v3d_irq_enable()
178 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); in v3d_irq_enable()
189 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); in v3d_irq_disable()
194 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); in v3d_irq_disable()
Dv3d_drv.h163 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) macro
Dv3d_gem.c84 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); in v3d_reset_v3d()