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/Linux-v4.19/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt23 - txen-skew-ps : Skew control of TX CTL pad
28 - txd0-skew-ps : Skew control of TX data 0 pad
29 - txd1-skew-ps : Skew control of TX data 1 pad
30 - txd2-skew-ps : Skew control of TX data 2 pad
31 - txd3-skew-ps : Skew control of TX data 3 pad
45 - txc-skew-ps : Skew control of TX clock pad
50 - txen-skew-ps : Skew control of TX CTL pad
55 - txd0-skew-ps : Skew control of TX data 0 pad
56 - txd1-skew-ps : Skew control of TX data 1 pad
57 - txd2-skew-ps : Skew control of TX data 2 pad
[all …]
Dxilinx_axienet.txt7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
21 - interrupts : Should be a list of two interrupt, TX and RX.
30 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
31 1 to enable partial TX checksum offload,
32 2 to enable full TX checksum offload
Dstmmac.txt54 - snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during
55 TX low-power mode
95 - Multiple TX Queues parameters: below the list of all the parameters to
96 configure the multiple TX queues:
97 - snps,tx-queues-to-use: number of TX queues to be used in the driver
98 - Choose one of these TX scheduling algorithms:
103 - For each TX queue
104 - snps,weight: TX queue weight (if using a DCB weight algorithm)
106 - snps,dcb-algorithm: TX queue will be working in DCB
107 - snps,avb-algorithm: TX queue will be working in AVB
[all …]
Dmeson-dwmac.txt31 - amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
34 When phy-mode is set to "rgmii" then the TX
38 or "rgmii-txid" the TX clock delay is already
41 the TX clock delay in the MAC to prevent the
Dethernet.txt29 * "rgmii" (RX and TX delays are added by the MAC when required)
30 * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
31 MAC should not add the RX or TX delays in this case)
34 * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
35 should not add an TX delay in this case)
/Linux-v4.19/drivers/spi/
Dspi-loopback-test.c94 .tx_buf = TX(0),
108 .tx_buf = TX(PAGE_SIZE - 4),
121 .tx_buf = TX(0),
146 .tx_buf = TX(0),
150 .tx_buf = TX(SPI_TEST_MAX_SIZE_HALF),
163 .tx_buf = TX(64),
167 .tx_buf = TX(0),
181 .tx_buf = TX(0),
184 .tx_buf = TX(64),
197 .tx_buf = TX(0),
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/display/bridge/
Ddw_hdmi.txt1 Synopsys DesignWare HDMI TX Encoder
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
Drenesas,dw-hdmi.txt1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
15 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
16 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
17 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
18 - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
/Linux-v4.19/Documentation/input/devices/
Dwalkera0701.rst24 Cable: (walkera TX to parport)
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
45 walkera0701 module, check dmesg for error messages. Connect TX to PC by
46 cable and run jstest /dev/input/js0 to see values from TX. If no value can
47 be changed by TX "joystick", check output from /proc/interrupts. Value for
48 (usually irq7) parport must increase if TX is on.
113 directly controlled from TX). Binary representations are the same as in first
/Linux-v4.19/Documentation/devicetree/bindings/dma/
Dste-dma40.txt60 bidirectional, i.e. the same for RX and TX operations:
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
112 50: Hash Accelerator 1 TX
113 51: memcpy TX (to be used by the DMA driver for memcpy operations)
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
125 63: Hash Accelerator 0 TX
/Linux-v4.19/Documentation/networking/
Dmac80211-auth-assoc-deauth.txt31 mac80211->driver: TX directed probe request
35 mac80211->driver: TX auth frame
39 mac80211->driver: TX auth frame
59 mac80211->driver: TX assoc
86 mac80211->driver: TX deauth/disassoc
Ddriver.txt41 And then at the end of your TX reclamation event handling:
69 For example, this means that it is not allowed for your TX
70 mitigation scheme to let TX packets "hang out" in the TX
71 ring unreclaimed forever if no new TX packets are sent.
Daf_xdp.rst25 TX ring. A socket can receive packets on the RX ring and it can send
26 packets on the TX ring. These rings are registered and sized with the
28 to have at least one of these rings for each socket. An RX or TX
30 UMEM. RX and TX can share the same UMEM so that a packet does not have
31 to be copied between RX and TX. Moreover, if a packet needs to be kept
48 space, for either TX or RX. Thus, the frame addrs appearing in the
50 TX ring. In summary, the RX and FILL rings are used for the RX path
51 and the TX and COMPLETION rings are used for the TX path.
65 process has to create its own socket with associated RX and TX rings,
124 TX. All rings are single-producer/single-consumer, so the user-space
[all …]
Dtlan.txt18 0e11 ae32 Compaq Netelligent 10/100 TX PCI UTP
21 0e11 ae40 Compaq Netelligent Dual 10/100 TX PCI UTP
22 0e11 ae43 Compaq Netelligent Integrated 10/100 TX UTP
23 0e11 b011 Compaq Netelligent 10/100 TX Embedded UTP
25 0e11 b030 Compaq Netelligent 10/100 TX UTP
/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
62 registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
/Linux-v4.19/drivers/usb/chipidea/
Dudc.c59 return num + ((dir == TX) ? 16 : 0); in hw_ep_bit()
122 (dir == TX) ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0); in hw_ep_disable()
138 if (dir == TX) { in hw_ep_enable()
170 u32 mask = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS; in hw_ep_get_halt()
220 u32 mask_xs = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS; in hw_ep_set_halt()
221 u32 mask_xr = (dir == TX) ? ENDPTCTRL_TXR : ENDPTCTRL_RXR; in hw_ep_set_halt()
359 if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) { in add_td_to_list()
399 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num; in _usb_addr()
451 if (hwreq->req.zero && hwreq->req.length && hwep->dir == TX in _hardware_enqueue()
587 if (hwep->dir == TX) { in _hardware_dequeue()
[all …]
/Linux-v4.19/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-nanopi-k2.dts195 gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
208 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
209 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
244 "Bluetooth UART TX", "Bluetooth UART RX",
Dmeson-gxbb-odroidc2.dts191 gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
204 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
205 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
/Linux-v4.19/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.txt13 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
81 S905 (GXBB) CVBS VDAC HDMI-TX
82 S905X (GXL) CVBS VDAC HDMI-TX
83 S905D (GXL) CVBS VDAC HDMI-TX
84 S912 (GXM) CVBS VDAC HDMI-TX
/Linux-v4.19/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
/Linux-v4.19/Documentation/devicetree/bindings/display/imx/
Dhdmi.txt1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
/Linux-v4.19/sound/soc/fsl/
Dfsl_ssi.c56 #define TX 1 macro
408 int dir = tx ? TX : RX; in fsl_ssi_config_enable()
428 srcr = vals[RX].srcr | vals[TX].srcr; in fsl_ssi_config_enable()
429 stcr = vals[RX].stcr | vals[TX].stcr; in fsl_ssi_config_enable()
430 sier = vals[RX].sier | vals[TX].sier; in fsl_ssi_config_enable()
509 int adir = tx ? RX : TX; in fsl_ssi_config_disable()
510 int dir = tx ? TX : RX; in fsl_ssi_config_disable()
589 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; in fsl_ssi_setup_regvals()
590 vals[TX].stcr = SSI_STCR_TFEN0; in fsl_ssi_setup_regvals()
591 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; in fsl_ssi_setup_regvals()
[all …]
Dfsl_sai.c375 if ((sai->synchronous[TX] && !sai->synchronous[RX]) || in fsl_sai_set_bclk()
382 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || in fsl_sai_set_bclk()
383 (tx && !sai->synchronous[TX])) { in fsl_sai_set_bclk()
453 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { in fsl_sai_hw_params()
462 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { in fsl_sai_hw_params()
514 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
854 sai->synchronous[TX] = false; in fsl_sai_probe()
869 sai->synchronous[TX] = true; in fsl_sai_probe()
873 sai->synchronous[TX] = false; in fsl_sai_probe()
/Linux-v4.19/Documentation/devicetree/bindings/mailbox/
Dhisilicon,hi6220-mailbox.txt23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
36 flag" mode or IRQ generated mode to acknowledge a TX
/Linux-v4.19/Documentation/devicetree/bindings/display/rockchip/
Ddw_hdmi-rockchip.txt1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

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