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Searched refs:REG_GET (Results 1 – 25 of 48) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.c133 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
134 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
135 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
147 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
380 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
384 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
385 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
386 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
400 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
401 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
[all …]
Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
684 REG_GET(DCSURF_FLIP_CONTROL, in hubp1_is_flip_pending()
687 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp1_is_flip_pending()
690 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp1_is_flip_pending()
812 REG_GET(HUBPRET_CONTROL, in hubp1_read_state()
843 REG_GET(BLANK_OFFSET_1, in hubp1_read_state()
846 REG_GET(DST_DIMENSIONS, in hubp1_read_state()
866 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp1_read_state()
870 REG_GET(VBLANK_PARAMETERS_1, in hubp1_read_state()
873 REG_GET(VBLANK_PARAMETERS_3, in hubp1_read_state()
[all …]
Ddcn10_optc.c382 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, in optc1_unblank_crtc()
609 REG_GET(OTG_STATUS_FRAME_COUNT, in optc1_get_vblank_counter()
648 REG_GET(OTG_NOM_VERT_POSITION, in optc1_get_position()
672 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, in optc1_did_triggered_reset_occur()
675 REG_GET(OTG_VERT_SYNC_CONTROL, in optc1_did_triggered_reset_occur()
699 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1200 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1213 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1220 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1223 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
[all …]
Ddcn10_dpp.c106 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
108 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
110 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
112 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
114 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
Ddcn10_hw_sequencer.c383 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode); in disable_vga()
384 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode); in disable_vga()
385 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode); in disable_vga()
386 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode); in disable_vga()
1508 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in mmhub_read_vm_system_aperture_settings()
1510 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_read_vm_system_aperture_settings()
1513 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_read_vm_system_aperture_settings()
1516 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_read_vm_system_aperture_settings()
1534 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); in mmhub_read_vm_context0_settings()
1535 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); in mmhub_read_vm_context0_settings()
[all …]
Ddcn10_dpp_cm.c235 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix()
490 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc()
667 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse()
757 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse()
827 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
Ddcn10_link_encoder.c494 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dcn10_is_dig_enabled()
1263 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1266 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dcn10_link_encoder_connect_dig_be_to_fe()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_abm.c66 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in get_current_backlight_16_bit()
67 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in get_current_backlight_16_bit()
70 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in get_current_backlight_16_bit()
71 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in get_current_backlight_16_bit()
335 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_immediate_disable()
349 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_abm_init_backlight()
377 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_init_backlight()
Ddce_mem_input.c588 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
625 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
682 REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending); in dce_mi_is_flip_pending()
Ddce_link_encoder.c549 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dce110_is_dig_enabled()
1309 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1312 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1332 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dce110_link_encoder_connect_dig_be_to_fe()
Ddce_aux.c258 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
274 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
291 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
Ddce_clock_source.c476 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); in dce110_get_pix_clk_dividers_helper()
648 REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled); in dce110_get_d_to_pixel_rate_in_hz()
653 REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase); in dce110_get_d_to_pixel_rate_in_hz()
654 REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo); in dce110_get_d_to_pixel_rate_in_hz()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
Dhw_hpd.c89 REG_GET(int_status, in get_value()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Di2c_hw_engine_dce110.c128 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
194 REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale); in get_speed()
239 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
245 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
407 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
421 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
531 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); in construct()
Daux_engine_dce110.c286 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
302 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
319 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
/Linux-v4.19/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.c54 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
126 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
131 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
140 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
147 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
155 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Dhdmi.h290 #define REG_GET(base, idx, start, end) \ macro
297 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
Ddsi.c122 #define REG_GET(dsi, idx, start, end) \ macro
530 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
537 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1762 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2325 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2336 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2358 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2385 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2404 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2551 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
Ddispc.c61 #define REG_GET(dispc, idx, start, end) \ macro
384 return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
750 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
758 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
763 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
1406 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1504 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1506 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
3357 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3771 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
[all …]
/Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.c55 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
127 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
132 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
141 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
148 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
156 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Dhdmi.h272 #define REG_GET(base, idx, start, end) \ macro
279 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
Ddsi.c121 #define REG_GET(dsidev, idx, start, end) \ macro
512 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
519 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1786 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2282 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2293 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2316 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2343 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2362 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2517 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
Ddispc.c59 #define REG_GET(idx, start, end) \ macro
275 return REG_GET(rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
595 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
603 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
608 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
1168 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); in dispc_init_fifos()
1259 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1261 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
2899 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); in dispc_ovl_enabled()
3790 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser_helper.c61 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()

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