59 #define REG_GET(idx, start, end) \  macro
275 	return REG_GET(rfld.reg, rfld.high, rfld.low);  in mgr_fld_read()
595 	return REG_GET(DISPC_CONTROL2, 6, 6) == 1;  in dispc_wb_go_busy()
603 	enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;  in dispc_wb_go()
608 	go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;  in dispc_wb_go()
1168 		size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);  in dispc_init_fifos()
1259 			REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),  in dispc_ovl_set_fifo_threshold()
1261 			REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),  in dispc_ovl_set_fifo_threshold()
2899 	return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);  in dispc_ovl_enabled()
3790 	cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);  in dispc_mgr_get_clock_div()
3791 	cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);  in dispc_mgr_get_clock_div()
4171 	if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {  in dispc_runtime_resume()