| /Linux-v4.19/include/dt-bindings/clock/ |
| D | rk3188-cru-common.h | 22 #define PLL_CPLL 3 macro
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| D | rk3128-cru.h | 22 #define PLL_CPLL 3 macro
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| D | rk3228-cru.h | 22 #define PLL_CPLL 3 macro
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| D | px30-cru.h | 9 #define PLL_CPLL 3 macro
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| D | rk3288-cru.h | 22 #define PLL_CPLL 3 macro
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| D | rk3328-cru.h | 22 #define PLL_CPLL 3 macro
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| D | rk3368-cru.h | 22 #define PLL_CPLL 4 macro
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| D | rk3399-cru.h | 23 #define PLL_CPLL 4 macro
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| /Linux-v4.19/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 226 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
237 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3128.c | 170 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3228.c | 181 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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| D | clk-rk3328.c | 228 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3368.c | 144 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
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| D | clk-rk3288.c | 212 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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| D | clk-px30.c | 194 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3399.c | 231 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
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| /Linux-v4.19/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-r88.dts | 212 assigned-clock-parents = <&cru PLL_CPLL>;
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| D | rk3399-gru.dtsi | 354 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3328.dtsi | 638 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3399.dtsi | 1294 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | rk3066a.dtsi | 117 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
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| D | rk322x.dtsi | 455 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
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| D | rk3288.dtsi | 857 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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