1 /*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/syscore_ops.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include "clk.h"
22
23 #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
24 #define RK3288_GRF_SOC_STATUS1 0x284
25
26 enum rk3288_plls {
27 apll, dpll, cpll, gpll, npll,
28 };
29
30 static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
31 RK3066_PLL_RATE(2208000000, 1, 92, 1),
32 RK3066_PLL_RATE(2184000000, 1, 91, 1),
33 RK3066_PLL_RATE(2160000000, 1, 90, 1),
34 RK3066_PLL_RATE(2136000000, 1, 89, 1),
35 RK3066_PLL_RATE(2112000000, 1, 88, 1),
36 RK3066_PLL_RATE(2088000000, 1, 87, 1),
37 RK3066_PLL_RATE(2064000000, 1, 86, 1),
38 RK3066_PLL_RATE(2040000000, 1, 85, 1),
39 RK3066_PLL_RATE(2016000000, 1, 84, 1),
40 RK3066_PLL_RATE(1992000000, 1, 83, 1),
41 RK3066_PLL_RATE(1968000000, 1, 82, 1),
42 RK3066_PLL_RATE(1944000000, 1, 81, 1),
43 RK3066_PLL_RATE(1920000000, 1, 80, 1),
44 RK3066_PLL_RATE(1896000000, 1, 79, 1),
45 RK3066_PLL_RATE(1872000000, 1, 78, 1),
46 RK3066_PLL_RATE(1848000000, 1, 77, 1),
47 RK3066_PLL_RATE(1824000000, 1, 76, 1),
48 RK3066_PLL_RATE(1800000000, 1, 75, 1),
49 RK3066_PLL_RATE(1776000000, 1, 74, 1),
50 RK3066_PLL_RATE(1752000000, 1, 73, 1),
51 RK3066_PLL_RATE(1728000000, 1, 72, 1),
52 RK3066_PLL_RATE(1704000000, 1, 71, 1),
53 RK3066_PLL_RATE(1680000000, 1, 70, 1),
54 RK3066_PLL_RATE(1656000000, 1, 69, 1),
55 RK3066_PLL_RATE(1632000000, 1, 68, 1),
56 RK3066_PLL_RATE(1608000000, 1, 67, 1),
57 RK3066_PLL_RATE(1560000000, 1, 65, 1),
58 RK3066_PLL_RATE(1512000000, 1, 63, 1),
59 RK3066_PLL_RATE(1488000000, 1, 62, 1),
60 RK3066_PLL_RATE(1464000000, 1, 61, 1),
61 RK3066_PLL_RATE(1440000000, 1, 60, 1),
62 RK3066_PLL_RATE(1416000000, 1, 59, 1),
63 RK3066_PLL_RATE(1392000000, 1, 58, 1),
64 RK3066_PLL_RATE(1368000000, 1, 57, 1),
65 RK3066_PLL_RATE(1344000000, 1, 56, 1),
66 RK3066_PLL_RATE(1320000000, 1, 55, 1),
67 RK3066_PLL_RATE(1296000000, 1, 54, 1),
68 RK3066_PLL_RATE(1272000000, 1, 53, 1),
69 RK3066_PLL_RATE(1248000000, 1, 52, 1),
70 RK3066_PLL_RATE(1224000000, 1, 51, 1),
71 RK3066_PLL_RATE(1200000000, 1, 50, 1),
72 RK3066_PLL_RATE(1188000000, 2, 99, 1),
73 RK3066_PLL_RATE(1176000000, 1, 49, 1),
74 RK3066_PLL_RATE(1128000000, 1, 47, 1),
75 RK3066_PLL_RATE(1104000000, 1, 46, 1),
76 RK3066_PLL_RATE(1008000000, 1, 84, 2),
77 RK3066_PLL_RATE( 912000000, 1, 76, 2),
78 RK3066_PLL_RATE( 891000000, 8, 594, 2),
79 RK3066_PLL_RATE( 888000000, 1, 74, 2),
80 RK3066_PLL_RATE( 816000000, 1, 68, 2),
81 RK3066_PLL_RATE( 798000000, 2, 133, 2),
82 RK3066_PLL_RATE( 792000000, 1, 66, 2),
83 RK3066_PLL_RATE( 768000000, 1, 64, 2),
84 RK3066_PLL_RATE( 742500000, 8, 495, 2),
85 RK3066_PLL_RATE( 696000000, 1, 58, 2),
86 RK3066_PLL_RATE( 600000000, 1, 50, 2),
87 RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
88 RK3066_PLL_RATE( 552000000, 1, 46, 2),
89 RK3066_PLL_RATE( 504000000, 1, 84, 4),
90 RK3066_PLL_RATE( 500000000, 3, 125, 2),
91 RK3066_PLL_RATE( 456000000, 1, 76, 4),
92 RK3066_PLL_RATE( 408000000, 1, 68, 4),
93 RK3066_PLL_RATE( 400000000, 3, 100, 2),
94 RK3066_PLL_RATE( 384000000, 2, 128, 4),
95 RK3066_PLL_RATE( 360000000, 1, 60, 4),
96 RK3066_PLL_RATE( 312000000, 1, 52, 4),
97 RK3066_PLL_RATE( 300000000, 1, 50, 4),
98 RK3066_PLL_RATE( 297000000, 2, 198, 8),
99 RK3066_PLL_RATE( 252000000, 1, 84, 8),
100 RK3066_PLL_RATE( 216000000, 1, 72, 8),
101 RK3066_PLL_RATE( 148500000, 2, 99, 8),
102 RK3066_PLL_RATE( 126000000, 1, 84, 16),
103 RK3066_PLL_RATE( 48000000, 1, 64, 32),
104 { /* sentinel */ },
105 };
106
107 #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
108 #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
109 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
110 #define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
111 #define RK3288_DIV_L2RAM_MASK 0x7
112 #define RK3288_DIV_L2RAM_SHIFT 0
113 #define RK3288_DIV_ATCLK_MASK 0x1f
114 #define RK3288_DIV_ATCLK_SHIFT 4
115 #define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
116 #define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
117
118 #define RK3288_CLKSEL0(_core_m0, _core_mp) \
119 { \
120 .reg = RK3288_CLKSEL_CON(0), \
121 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
122 RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
123 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
124 RK3288_DIV_ACLK_CORE_MP_SHIFT), \
125 }
126 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
127 { \
128 .reg = RK3288_CLKSEL_CON(37), \
129 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
130 RK3288_DIV_L2RAM_SHIFT) | \
131 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
132 RK3288_DIV_ATCLK_SHIFT) | \
133 HIWORD_UPDATE(_pclk_dbg_pre, \
134 RK3288_DIV_PCLK_DBGPRE_MASK, \
135 RK3288_DIV_PCLK_DBGPRE_SHIFT), \
136 }
137
138 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
139 { \
140 .prate = _prate, \
141 .divs = { \
142 RK3288_CLKSEL0(_core_m0, _core_mp), \
143 RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
144 }, \
145 }
146
147 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
148 RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
149 RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
150 RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
151 RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
152 RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
153 RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
154 RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
155 RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
156 RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
157 RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
158 RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
159 RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
160 RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
161 RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
162 };
163
164 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
165 .core_reg = RK3288_CLKSEL_CON(0),
166 .div_core_shift = 8,
167 .div_core_mask = 0x1f,
168 .mux_core_alt = 1,
169 .mux_core_main = 0,
170 .mux_core_shift = 15,
171 .mux_core_mask = 0x1,
172 };
173
174 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
175 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
176 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
177 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
178
179 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
180 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
181 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
182 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
183 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
184
185 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
186 PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
187 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
188 PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
189 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
190 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
191 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
192 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
193 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
194 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
195 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
196 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
197 PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
198 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
199 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
200
201 PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" };
202 PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
203 "sclk_otgphy0_480m" };
204 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
205 PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
206
207 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
208 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
209 RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
210 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
211 RK3288_MODE_CON, 4, 5, 0, NULL),
212 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
213 RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
214 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
215 RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
216 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
217 RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
218 };
219
220 static struct clk_div_table div_hclk_cpu_t[] = {
221 { .val = 0, .div = 1 },
222 { .val = 1, .div = 2 },
223 { .val = 3, .div = 4 },
224 { /* sentinel */},
225 };
226
227 #define MFLAGS CLK_MUX_HIWORD_MASK
228 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
229 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
230 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
231
232 static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
233 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
234 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
235
236 static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
237 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
238 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
239
240 static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
241 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
242 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
243
244 static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
245 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
246 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
247
248 static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
249 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
250 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
251
252 static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
253 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
254 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
255
256 static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
257 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
258 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
259
260 static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
261 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
262 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
263
264 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
265 /*
266 * Clock-Architecture Diagram 1
267 */
268
269 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
270 RK3288_CLKGATE_CON(0), 1, GFLAGS),
271 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
272 RK3288_CLKGATE_CON(0), 2, GFLAGS),
273
274 COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
275 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
276 RK3288_CLKGATE_CON(12), 0, GFLAGS),
277 COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
278 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
279 RK3288_CLKGATE_CON(12), 1, GFLAGS),
280 COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
281 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
282 RK3288_CLKGATE_CON(12), 2, GFLAGS),
283 COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
284 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
285 RK3288_CLKGATE_CON(12), 3, GFLAGS),
286 COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
287 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
288 RK3288_CLKGATE_CON(12), 4, GFLAGS),
289 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
290 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
291 RK3288_CLKGATE_CON(12), 5, GFLAGS),
292 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
293 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
294 RK3288_CLKGATE_CON(12), 6, GFLAGS),
295 COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
296 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
297 RK3288_CLKGATE_CON(12), 7, GFLAGS),
298 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
299 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
300 RK3288_CLKGATE_CON(12), 8, GFLAGS),
301 GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
302 RK3288_CLKGATE_CON(12), 9, GFLAGS),
303 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
304 RK3288_CLKGATE_CON(12), 10, GFLAGS),
305 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
306 RK3288_CLKGATE_CON(12), 11, GFLAGS),
307
308 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
309 RK3288_CLKGATE_CON(0), 8, GFLAGS),
310 GATE(0, "gpll_ddr", "gpll", 0,
311 RK3288_CLKGATE_CON(0), 9, GFLAGS),
312 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
313 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
314 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
315
316 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
317 RK3288_CLKGATE_CON(0), 10, GFLAGS),
318 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
319 RK3288_CLKGATE_CON(0), 11, GFLAGS),
320 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
321 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
322 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
323 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
324 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
325 RK3288_CLKGATE_CON(0), 3, GFLAGS),
326 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
327 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
328 RK3288_CLKGATE_CON(0), 5, GFLAGS),
329 COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
330 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
331 RK3288_CLKGATE_CON(0), 4, GFLAGS),
332 GATE(0, "c2c_host", "aclk_cpu_src", 0,
333 RK3288_CLKGATE_CON(13), 8, GFLAGS),
334 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
335 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
336 RK3288_CLKGATE_CON(5), 4, GFLAGS),
337 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
338 RK3288_CLKGATE_CON(0), 7, GFLAGS),
339
340 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
341
342 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
343 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
344 RK3288_CLKGATE_CON(4), 1, GFLAGS),
345 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
346 RK3288_CLKSEL_CON(8), 0,
347 RK3288_CLKGATE_CON(4), 2, GFLAGS,
348 &rk3288_i2s_fracmux),
349 COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
350 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
351 RK3288_CLKGATE_CON(4), 0, GFLAGS),
352 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
353 RK3288_CLKGATE_CON(4), 3, GFLAGS),
354
355 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
356 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
357 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
358 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
359 RK3288_CLKGATE_CON(4), 4, GFLAGS),
360 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
361 RK3288_CLKSEL_CON(9), 0,
362 RK3288_CLKGATE_CON(4), 5, GFLAGS,
363 &rk3288_spdif_fracmux),
364 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
365 RK3288_CLKGATE_CON(4), 6, GFLAGS),
366 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
367 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
368 RK3288_CLKGATE_CON(4), 7, GFLAGS),
369 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
370 RK3288_CLKSEL_CON(41), 0,
371 RK3288_CLKGATE_CON(4), 8, GFLAGS,
372 &rk3288_spdif_8ch_fracmux),
373 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
374 RK3288_CLKGATE_CON(4), 9, GFLAGS),
375
376 GATE(0, "sclk_acc_efuse", "xin24m", 0,
377 RK3288_CLKGATE_CON(0), 12, GFLAGS),
378
379 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
380 RK3288_CLKGATE_CON(1), 0, GFLAGS),
381 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
382 RK3288_CLKGATE_CON(1), 1, GFLAGS),
383 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
384 RK3288_CLKGATE_CON(1), 2, GFLAGS),
385 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
386 RK3288_CLKGATE_CON(1), 3, GFLAGS),
387 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
388 RK3288_CLKGATE_CON(1), 4, GFLAGS),
389 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
390 RK3288_CLKGATE_CON(1), 5, GFLAGS),
391
392 /*
393 * Clock-Architecture Diagram 2
394 */
395
396 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
397 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
398 RK3288_CLKGATE_CON(3), 9, GFLAGS),
399 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
400 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
401 RK3288_CLKGATE_CON(3), 11, GFLAGS),
402 MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, 0,
403 RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
404 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
405 RK3288_CLKGATE_CON(9), 0, GFLAGS),
406
407 FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
408 RK3288_CLKGATE_CON(3), 10, GFLAGS),
409
410 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
411 RK3288_CLKGATE_CON(9), 1, GFLAGS),
412
413 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
414 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
415 RK3288_CLKGATE_CON(3), 0, GFLAGS),
416 DIV(0, "hclk_vio", "aclk_vio0", 0,
417 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
418 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
419 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
420 RK3288_CLKGATE_CON(3), 2, GFLAGS),
421
422 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
423 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
424 RK3288_CLKGATE_CON(3), 5, GFLAGS),
425 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
426 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
427 RK3288_CLKGATE_CON(3), 4, GFLAGS),
428
429 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
430 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
431 RK3288_CLKGATE_CON(3), 1, GFLAGS),
432 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
433 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
434 RK3288_CLKGATE_CON(3), 3, GFLAGS),
435
436 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
437 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
438 RK3288_CLKGATE_CON(3), 12, GFLAGS),
439 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
440 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
441 RK3288_CLKGATE_CON(3), 13, GFLAGS),
442
443 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
444 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
445 RK3288_CLKGATE_CON(3), 14, GFLAGS),
446 COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
447 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
448 RK3288_CLKGATE_CON(3), 15, GFLAGS),
449
450 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
451 RK3288_CLKGATE_CON(5), 12, GFLAGS),
452 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
453 RK3288_CLKGATE_CON(5), 11, GFLAGS),
454
455 COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
456 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
457 RK3288_CLKGATE_CON(13), 13, GFLAGS),
458 DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
459 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
460
461 COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
462 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
463 RK3288_CLKGATE_CON(13), 14, GFLAGS),
464 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
465 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
466 RK3288_CLKGATE_CON(13), 15, GFLAGS),
467
468 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
469 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
470 RK3288_CLKGATE_CON(3), 7, GFLAGS),
471 COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
472 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
473
474 DIV(0, "pclk_pd_alive", "gpll", 0,
475 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
476 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
477 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
478 RK3288_CLKGATE_CON(5), 8, GFLAGS),
479
480 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
481 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
482 RK3288_CLKGATE_CON(5), 7, GFLAGS),
483
484 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
485 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
486 RK3288_CLKGATE_CON(2), 0, GFLAGS),
487 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
488 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
489 RK3288_CLKGATE_CON(2), 3, GFLAGS),
490 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
491 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
492 RK3288_CLKGATE_CON(2), 2, GFLAGS),
493 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
494 RK3288_CLKGATE_CON(2), 1, GFLAGS),
495
496 /*
497 * Clock-Architecture Diagram 3
498 */
499
500 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
501 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
502 RK3288_CLKGATE_CON(2), 9, GFLAGS),
503 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
504 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
505 RK3288_CLKGATE_CON(2), 10, GFLAGS),
506 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
507 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
508 RK3288_CLKGATE_CON(2), 11, GFLAGS),
509
510 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
511 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
512 RK3288_CLKGATE_CON(13), 0, GFLAGS),
513 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
514 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
515 RK3288_CLKGATE_CON(13), 1, GFLAGS),
516 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
517 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
518 RK3288_CLKGATE_CON(13), 2, GFLAGS),
519 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
520 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
521 RK3288_CLKGATE_CON(13), 3, GFLAGS),
522
523 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
524 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
525
526 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
527 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
528
529 MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
530 MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
531
532 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
533 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
534
535 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
536 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
537 RK3288_CLKGATE_CON(4), 11, GFLAGS),
538 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
539 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
540 RK3288_CLKGATE_CON(4), 10, GFLAGS),
541
542 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
543 RK3288_CLKGATE_CON(13), 4, GFLAGS),
544 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
545 RK3288_CLKGATE_CON(13), 5, GFLAGS),
546 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
547 RK3288_CLKGATE_CON(13), 6, GFLAGS),
548 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
549 RK3288_CLKGATE_CON(13), 7, GFLAGS),
550
551 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
552 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
553 RK3288_CLKGATE_CON(2), 7, GFLAGS),
554
555 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
556 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
557 RK3288_CLKGATE_CON(2), 8, GFLAGS),
558
559 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
560 RK3288_CLKGATE_CON(5), 13, GFLAGS),
561
562 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
563 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
564 RK3288_CLKGATE_CON(5), 5, GFLAGS),
565 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
566 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
567 RK3288_CLKGATE_CON(5), 6, GFLAGS),
568
569 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
570 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
571 RK3288_CLKGATE_CON(1), 8, GFLAGS),
572 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
573 RK3288_CLKSEL_CON(17), 0,
574 RK3288_CLKGATE_CON(1), 9, GFLAGS,
575 &rk3288_uart0_fracmux),
576 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
577 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
578 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
579 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
580 RK3288_CLKGATE_CON(1), 10, GFLAGS),
581 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
582 RK3288_CLKSEL_CON(18), 0,
583 RK3288_CLKGATE_CON(1), 11, GFLAGS,
584 &rk3288_uart1_fracmux),
585 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
586 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
587 RK3288_CLKGATE_CON(1), 12, GFLAGS),
588 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
589 RK3288_CLKSEL_CON(19), 0,
590 RK3288_CLKGATE_CON(1), 13, GFLAGS,
591 &rk3288_uart2_fracmux),
592 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
593 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
594 RK3288_CLKGATE_CON(1), 14, GFLAGS),
595 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
596 RK3288_CLKSEL_CON(20), 0,
597 RK3288_CLKGATE_CON(1), 15, GFLAGS,
598 &rk3288_uart3_fracmux),
599 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
600 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
601 RK3288_CLKGATE_CON(2), 12, GFLAGS),
602 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
603 RK3288_CLKSEL_CON(7), 0,
604 RK3288_CLKGATE_CON(2), 13, GFLAGS,
605 &rk3288_uart4_fracmux),
606
607 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
608 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
609 RK3288_CLKGATE_CON(2), 5, GFLAGS),
610 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
611 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
612 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
613 RK3288_CLKGATE_CON(5), 3, GFLAGS),
614 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
615 RK3288_CLKGATE_CON(5), 2, GFLAGS),
616 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
617 RK3288_CLKGATE_CON(5), 0, GFLAGS),
618 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
619 RK3288_CLKGATE_CON(5), 1, GFLAGS),
620
621 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
622 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
623 RK3288_CLKGATE_CON(2), 6, GFLAGS),
624 MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
625 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
626 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
627 RK3288_CLKSEL_CON(22), 7, IFLAGS),
628
629 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
630 RK3288_CLKGATE_CON(4), 14, GFLAGS),
631
632 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
633 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
634 RK3288_CLKGATE_CON(5), 14, GFLAGS),
635 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
636 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
637 RK3288_CLKGATE_CON(3), 6, GFLAGS),
638 GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
639 RK3288_CLKGATE_CON(13), 9, GFLAGS),
640 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
641 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
642 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
643 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
644
645 /*
646 * Clock-Architecture Diagram 4
647 */
648
649 /* aclk_cpu gates */
650 GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
651 GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
652 GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
653 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
654 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
655 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
656 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
657 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
658
659 /* hclk_cpu gates */
660 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
661 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
662 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
663 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
664 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
665
666 /* pclk_cpu gates */
667 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
668 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
669 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
670 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
671 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
672 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
673 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
674 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
675 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
676 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
677 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
678 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
679 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
680
681 /* ddrctrl [DDR Controller PHY clock] gates */
682 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
683 GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
684
685 /* ddrphy gates */
686 GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
687 GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
688
689 /* aclk_peri gates */
690 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
691 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
692 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
693 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
694 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
695 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
696
697 /* hclk_peri gates */
698 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
699 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
700 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
701 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
702 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
703 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
704 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
705 GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
706 GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
707 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
708 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
709 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
710 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
711 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
712 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
713 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
714 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
715 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
716
717 /* pclk_peri gates */
718 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
719 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
720 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
721 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
722 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
723 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
724 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
725 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
726 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
727 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
728 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
729 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
730 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
731 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
732 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
733 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
734 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
735
736 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
737 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
738 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
739 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
740 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
741
742 /* sclk_gpu gates */
743 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
744
745 /* pclk_pd_alive gates */
746 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
747 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
748 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
749 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
750 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
751 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
752 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
753 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
754 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
755 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
756
757 /* pclk_pd_pmu gates */
758 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
759 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
760 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
761 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
762 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
763
764 /* hclk_vio gates */
765 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
766 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
767 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
768 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
769 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
770 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
771 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
772 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
773 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
774 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
775 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
776 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
777 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
778 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
779 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
780 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
781
782 /* aclk_vio0 gates */
783 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
784 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
785 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
786 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
787
788 /* aclk_vio1 gates */
789 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
790 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
791 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
792
793 /* aclk_rga_pre gates */
794 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
795 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
796
797 /*
798 * Other ungrouped clocks.
799 */
800
801 GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
802 INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
803 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
804 INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
805 };
806
807 static const char *const rk3288_critical_clocks[] __initconst = {
808 "aclk_cpu",
809 "aclk_peri",
810 "aclk_peri_niu",
811 "aclk_vio0_niu",
812 "aclk_vio1_niu",
813 "aclk_rga_niu",
814 "hclk_peri",
815 "hclk_vio_niu",
816 "pclk_alive_niu",
817 "pclk_pd_pmu",
818 "pclk_pmu_niu",
819 "pclk_core_niu",
820 "pclk_ddrupctl0",
821 "pclk_publ0",
822 "pclk_ddrupctl1",
823 "pclk_publ1",
824 "pmu_hclk_otg0",
825 };
826
827 static void __iomem *rk3288_cru_base;
828
829 /*
830 * Some CRU registers will be reset in maskrom when the system
831 * wakes up from fastboot.
832 * So save them before suspend, restore them after resume.
833 */
834 static const int rk3288_saved_cru_reg_ids[] = {
835 RK3288_MODE_CON,
836 RK3288_CLKSEL_CON(0),
837 RK3288_CLKSEL_CON(1),
838 RK3288_CLKSEL_CON(10),
839 RK3288_CLKSEL_CON(33),
840 RK3288_CLKSEL_CON(37),
841 };
842
843 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
844
rk3288_clk_suspend(void)845 static int rk3288_clk_suspend(void)
846 {
847 int i, reg_id;
848
849 for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
850 reg_id = rk3288_saved_cru_reg_ids[i];
851
852 rk3288_saved_cru_regs[i] =
853 readl_relaxed(rk3288_cru_base + reg_id);
854 }
855
856 /*
857 * Switch PLLs other than DPLL (for SDRAM) to slow mode to
858 * avoid crashes on resume. The Mask ROM on the system will
859 * put APLL, CPLL, and GPLL into slow mode at resume time
860 * anyway (which is why we restore them), but we might not
861 * even make it to the Mask ROM if this isn't done at suspend
862 * time.
863 *
864 * NOTE: only APLL truly matters here, but we'll do them all.
865 */
866
867 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
868
869 return 0;
870 }
871
rk3288_clk_resume(void)872 static void rk3288_clk_resume(void)
873 {
874 int i, reg_id;
875
876 for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
877 reg_id = rk3288_saved_cru_reg_ids[i];
878
879 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
880 rk3288_cru_base + reg_id);
881 }
882 }
883
rk3288_clk_shutdown(void)884 static void rk3288_clk_shutdown(void)
885 {
886 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
887 }
888
889 static struct syscore_ops rk3288_clk_syscore_ops = {
890 .suspend = rk3288_clk_suspend,
891 .resume = rk3288_clk_resume,
892 };
893
rk3288_clk_init(struct device_node * np)894 static void __init rk3288_clk_init(struct device_node *np)
895 {
896 struct rockchip_clk_provider *ctx;
897 struct clk *clk;
898
899 rk3288_cru_base = of_iomap(np, 0);
900 if (!rk3288_cru_base) {
901 pr_err("%s: could not map cru region\n", __func__);
902 return;
903 }
904
905 ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
906 if (IS_ERR(ctx)) {
907 pr_err("%s: rockchip clk init failed\n", __func__);
908 iounmap(rk3288_cru_base);
909 return;
910 }
911
912 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
913 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
914 if (IS_ERR(clk))
915 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
916 __func__, PTR_ERR(clk));
917 else
918 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
919
920 rockchip_clk_register_plls(ctx, rk3288_pll_clks,
921 ARRAY_SIZE(rk3288_pll_clks),
922 RK3288_GRF_SOC_STATUS1);
923 rockchip_clk_register_branches(ctx, rk3288_clk_branches,
924 ARRAY_SIZE(rk3288_clk_branches));
925 rockchip_clk_protect_critical(rk3288_critical_clocks,
926 ARRAY_SIZE(rk3288_critical_clocks));
927
928 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
929 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
930 &rk3288_cpuclk_data, rk3288_cpuclk_rates,
931 ARRAY_SIZE(rk3288_cpuclk_rates));
932
933 rockchip_register_softrst(np, 12,
934 rk3288_cru_base + RK3288_SOFTRST_CON(0),
935 ROCKCHIP_SOFTRST_HIWORD_MASK);
936
937 rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
938 rk3288_clk_shutdown);
939 register_syscore_ops(&rk3288_clk_syscore_ops);
940
941 rockchip_clk_of_add_provider(np, ctx);
942 }
943 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
944
