1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3228-cru.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 aliases { 17 serial0 = &uart0; 18 serial1 = &uart1; 19 serial2 = &uart2; 20 spi0 = &spi0; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@f00 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a7"; 30 reg = <0xf00>; 31 resets = <&cru SRST_CORE0>; 32 operating-points-v2 = <&cpu0_opp_table>; 33 #cooling-cells = <2>; /* min followed by max */ 34 clock-latency = <40000>; 35 clocks = <&cru ARMCLK>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@f01 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a7"; 42 reg = <0xf01>; 43 resets = <&cru SRST_CORE1>; 44 operating-points-v2 = <&cpu0_opp_table>; 45 #cooling-cells = <2>; /* min followed by max */ 46 enable-method = "psci"; 47 }; 48 49 cpu2: cpu@f02 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a7"; 52 reg = <0xf02>; 53 resets = <&cru SRST_CORE2>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 enable-method = "psci"; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 #cooling-cells = <2>; /* min followed by max */ 66 enable-method = "psci"; 67 }; 68 }; 69 70 cpu0_opp_table: opp_table0 { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 74 opp-408000000 { 75 opp-hz = /bits/ 64 <408000000>; 76 opp-microvolt = <950000>; 77 clock-latency-ns = <40000>; 78 opp-suspend; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <975000>; 83 }; 84 opp-816000000 { 85 opp-hz = /bits/ 64 <816000000>; 86 opp-microvolt = <1000000>; 87 }; 88 opp-1008000000 { 89 opp-hz = /bits/ 64 <1008000000>; 90 opp-microvolt = <1175000>; 91 }; 92 opp-1200000000 { 93 opp-hz = /bits/ 64 <1200000000>; 94 opp-microvolt = <1275000>; 95 }; 96 }; 97 98 amba { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 pdma: pdma@110f0000 { 105 compatible = "arm,pl330", "arm,primecell"; 106 reg = <0x110f0000 0x4000>; 107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 109 #dma-cells = <1>; 110 clocks = <&cru ACLK_DMAC>; 111 clock-names = "apb_pclk"; 112 }; 113 }; 114 115 arm-pmu { 116 compatible = "arm,cortex-a7-pmu"; 117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 122 }; 123 124 psci { 125 compatible = "arm,psci-1.0", "arm,psci-0.2"; 126 method = "smc"; 127 }; 128 129 timer { 130 compatible = "arm,armv7-timer"; 131 arm,cpu-registers-not-fw-configured; 132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clock-frequency = <24000000>; 137 }; 138 139 xin24m: oscillator { 140 compatible = "fixed-clock"; 141 clock-frequency = <24000000>; 142 clock-output-names = "xin24m"; 143 #clock-cells = <0>; 144 }; 145 146 i2s1: i2s1@100b0000 { 147 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 148 reg = <0x100b0000 0x4000>; 149 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 clock-names = "i2s_clk", "i2s_hclk"; 153 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 154 dmas = <&pdma 14>, <&pdma 15>; 155 dma-names = "tx", "rx"; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&i2s1_bus>; 158 status = "disabled"; 159 }; 160 161 i2s0: i2s0@100c0000 { 162 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 163 reg = <0x100c0000 0x4000>; 164 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clock-names = "i2s_clk", "i2s_hclk"; 168 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 169 dmas = <&pdma 11>, <&pdma 12>; 170 dma-names = "tx", "rx"; 171 status = "disabled"; 172 }; 173 174 spdif: spdif@100d0000 { 175 compatible = "rockchip,rk3228-spdif"; 176 reg = <0x100d0000 0x1000>; 177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 179 clock-names = "mclk", "hclk"; 180 dmas = <&pdma 10>; 181 dma-names = "tx"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&spdif_tx>; 184 status = "disabled"; 185 }; 186 187 i2s2: i2s2@100e0000 { 188 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 189 reg = <0x100e0000 0x4000>; 190 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 clock-names = "i2s_clk", "i2s_hclk"; 194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 195 dmas = <&pdma 0>, <&pdma 1>; 196 dma-names = "tx", "rx"; 197 status = "disabled"; 198 }; 199 200 grf: syscon@11000000 { 201 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 202 reg = <0x11000000 0x1000>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 206 io_domains: io-domains { 207 compatible = "rockchip,rk3228-io-voltage-domain"; 208 status = "disabled"; 209 }; 210 211 u2phy0: usb2-phy@760 { 212 compatible = "rockchip,rk3228-usb2phy"; 213 reg = <0x0760 0x0c>; 214 clocks = <&cru SCLK_OTGPHY0>; 215 clock-names = "phyclk"; 216 clock-output-names = "usb480m_phy0"; 217 #clock-cells = <0>; 218 status = "disabled"; 219 220 u2phy0_otg: otg-port { 221 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 224 interrupt-names = "otg-bvalid", "otg-id", 225 "linestate"; 226 #phy-cells = <0>; 227 status = "disabled"; 228 }; 229 230 u2phy0_host: host-port { 231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "linestate"; 233 #phy-cells = <0>; 234 status = "disabled"; 235 }; 236 }; 237 238 u2phy1: usb2-phy@800 { 239 compatible = "rockchip,rk3228-usb2phy"; 240 reg = <0x0800 0x0c>; 241 clocks = <&cru SCLK_OTGPHY1>; 242 clock-names = "phyclk"; 243 clock-output-names = "usb480m_phy1"; 244 #clock-cells = <0>; 245 status = "disabled"; 246 247 u2phy1_otg: otg-port { 248 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-names = "linestate"; 250 #phy-cells = <0>; 251 status = "disabled"; 252 }; 253 254 u2phy1_host: host-port { 255 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "linestate"; 257 #phy-cells = <0>; 258 status = "disabled"; 259 }; 260 }; 261 }; 262 263 uart0: serial@11010000 { 264 compatible = "snps,dw-apb-uart"; 265 reg = <0x11010000 0x100>; 266 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 267 clock-frequency = <24000000>; 268 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 269 clock-names = "baudclk", "apb_pclk"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 272 reg-shift = <2>; 273 reg-io-width = <4>; 274 status = "disabled"; 275 }; 276 277 uart1: serial@11020000 { 278 compatible = "snps,dw-apb-uart"; 279 reg = <0x11020000 0x100>; 280 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 281 clock-frequency = <24000000>; 282 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 283 clock-names = "baudclk", "apb_pclk"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&uart1_xfer>; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 status = "disabled"; 289 }; 290 291 uart2: serial@11030000 { 292 compatible = "snps,dw-apb-uart"; 293 reg = <0x11030000 0x100>; 294 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 295 clock-frequency = <24000000>; 296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 297 clock-names = "baudclk", "apb_pclk"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&uart2_xfer>; 300 reg-shift = <2>; 301 reg-io-width = <4>; 302 status = "disabled"; 303 }; 304 305 efuse: efuse@11040000 { 306 compatible = "rockchip,rk3228-efuse"; 307 reg = <0x11040000 0x20>; 308 clocks = <&cru PCLK_EFUSE_256>; 309 clock-names = "pclk_efuse"; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 313 /* Data cells */ 314 efuse_id: id@7 { 315 reg = <0x7 0x10>; 316 }; 317 cpu_leakage: cpu_leakage@17 { 318 reg = <0x17 0x1>; 319 }; 320 }; 321 322 i2c0: i2c@11050000 { 323 compatible = "rockchip,rk3228-i2c"; 324 reg = <0x11050000 0x1000>; 325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clock-names = "i2c"; 329 clocks = <&cru PCLK_I2C0>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c0_xfer>; 332 status = "disabled"; 333 }; 334 335 i2c1: i2c@11060000 { 336 compatible = "rockchip,rk3228-i2c"; 337 reg = <0x11060000 0x1000>; 338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clock-names = "i2c"; 342 clocks = <&cru PCLK_I2C1>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c1_xfer>; 345 status = "disabled"; 346 }; 347 348 i2c2: i2c@11070000 { 349 compatible = "rockchip,rk3228-i2c"; 350 reg = <0x11070000 0x1000>; 351 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clock-names = "i2c"; 355 clocks = <&cru PCLK_I2C2>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&i2c2_xfer>; 358 status = "disabled"; 359 }; 360 361 i2c3: i2c@11080000 { 362 compatible = "rockchip,rk3228-i2c"; 363 reg = <0x11080000 0x1000>; 364 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clock-names = "i2c"; 368 clocks = <&cru PCLK_I2C3>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&i2c3_xfer>; 371 status = "disabled"; 372 }; 373 374 spi0: spi@11090000 { 375 compatible = "rockchip,rk3228-spi"; 376 reg = <0x11090000 0x1000>; 377 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 381 clock-names = "spiclk", "apb_pclk"; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 384 status = "disabled"; 385 }; 386 387 wdt: watchdog@110a0000 { 388 compatible = "snps,dw-wdt"; 389 reg = <0x110a0000 0x100>; 390 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cru PCLK_CPU>; 392 status = "disabled"; 393 }; 394 395 pwm0: pwm@110b0000 { 396 compatible = "rockchip,rk3288-pwm"; 397 reg = <0x110b0000 0x10>; 398 #pwm-cells = <3>; 399 clocks = <&cru PCLK_PWM>; 400 clock-names = "pwm"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pwm0_pin>; 403 status = "disabled"; 404 }; 405 406 pwm1: pwm@110b0010 { 407 compatible = "rockchip,rk3288-pwm"; 408 reg = <0x110b0010 0x10>; 409 #pwm-cells = <3>; 410 clocks = <&cru PCLK_PWM>; 411 clock-names = "pwm"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pwm1_pin>; 414 status = "disabled"; 415 }; 416 417 pwm2: pwm@110b0020 { 418 compatible = "rockchip,rk3288-pwm"; 419 reg = <0x110b0020 0x10>; 420 #pwm-cells = <3>; 421 clocks = <&cru PCLK_PWM>; 422 clock-names = "pwm"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pwm2_pin>; 425 status = "disabled"; 426 }; 427 428 pwm3: pwm@110b0030 { 429 compatible = "rockchip,rk3288-pwm"; 430 reg = <0x110b0030 0x10>; 431 #pwm-cells = <2>; 432 clocks = <&cru PCLK_PWM>; 433 clock-names = "pwm"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pwm3_pin>; 436 status = "disabled"; 437 }; 438 439 timer: timer@110c0000 { 440 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; 441 reg = <0x110c0000 0x20>; 442 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&xin24m>, <&cru PCLK_TIMER>; 444 clock-names = "timer", "pclk"; 445 }; 446 447 cru: clock-controller@110e0000 { 448 compatible = "rockchip,rk3228-cru"; 449 reg = <0x110e0000 0x1000>; 450 rockchip,grf = <&grf>; 451 #clock-cells = <1>; 452 #reset-cells = <1>; 453 assigned-clocks = 454 <&cru PLL_GPLL>, <&cru ARMCLK>, 455 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 456 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 457 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 458 <&cru PCLK_CPU>; 459 assigned-clock-rates = 460 <594000000>, <816000000>, 461 <500000000>, <150000000>, 462 <150000000>, <75000000>, 463 <150000000>, <150000000>, 464 <75000000>; 465 }; 466 467 thermal-zones { 468 cpu_thermal: cpu-thermal { 469 polling-delay-passive = <100>; /* milliseconds */ 470 polling-delay = <5000>; /* milliseconds */ 471 472 thermal-sensors = <&tsadc 0>; 473 474 trips { 475 cpu_alert0: cpu_alert0 { 476 temperature = <70000>; /* millicelsius */ 477 hysteresis = <2000>; /* millicelsius */ 478 type = "passive"; 479 }; 480 cpu_alert1: cpu_alert1 { 481 temperature = <75000>; /* millicelsius */ 482 hysteresis = <2000>; /* millicelsius */ 483 type = "passive"; 484 }; 485 cpu_crit: cpu_crit { 486 temperature = <90000>; /* millicelsius */ 487 hysteresis = <2000>; /* millicelsius */ 488 type = "critical"; 489 }; 490 }; 491 492 cooling-maps { 493 map0 { 494 trip = <&cpu_alert0>; 495 cooling-device = 496 <&cpu0 THERMAL_NO_LIMIT 6>; 497 }; 498 map1 { 499 trip = <&cpu_alert1>; 500 cooling-device = 501 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 502 }; 503 }; 504 }; 505 }; 506 507 tsadc: tsadc@11150000 { 508 compatible = "rockchip,rk3228-tsadc"; 509 reg = <0x11150000 0x100>; 510 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 512 clock-names = "tsadc", "apb_pclk"; 513 assigned-clocks = <&cru SCLK_TSADC>; 514 assigned-clock-rates = <32768>; 515 resets = <&cru SRST_TSADC>; 516 reset-names = "tsadc-apb"; 517 pinctrl-names = "init", "default", "sleep"; 518 pinctrl-0 = <&otp_gpio>; 519 pinctrl-1 = <&otp_out>; 520 pinctrl-2 = <&otp_gpio>; 521 #thermal-sensor-cells = <0>; 522 rockchip,hw-tshut-temp = <95000>; 523 status = "disabled"; 524 }; 525 526 gpu: gpu@20000000 { 527 compatible = "rockchip,rk3228-mali", "arm,mali-400"; 528 reg = <0x20000000 0x10000>; 529 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 535 interrupt-names = "gp", 536 "gpmmu", 537 "pp0", 538 "ppmmu0", 539 "pp1", 540 "ppmmu1"; 541 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 542 clock-names = "core", "bus"; 543 resets = <&cru SRST_GPU_A>; 544 status = "disabled"; 545 }; 546 547 vpu_mmu: iommu@20020800 { 548 compatible = "rockchip,iommu"; 549 reg = <0x20020800 0x100>; 550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "vpu_mmu"; 552 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 553 clock-names = "aclk", "iface"; 554 iommu-cells = <0>; 555 status = "disabled"; 556 }; 557 558 vdec_mmu: iommu@20030480 { 559 compatible = "rockchip,iommu"; 560 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 561 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "vdec_mmu"; 563 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 564 clock-names = "aclk", "iface"; 565 iommu-cells = <0>; 566 status = "disabled"; 567 }; 568 569 vop_mmu: iommu@20053f00 { 570 compatible = "rockchip,iommu"; 571 reg = <0x20053f00 0x100>; 572 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "vop_mmu"; 574 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 575 clock-names = "aclk", "iface"; 576 iommu-cells = <0>; 577 status = "disabled"; 578 }; 579 580 iep_mmu: iommu@20070800 { 581 compatible = "rockchip,iommu"; 582 reg = <0x20070800 0x100>; 583 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "iep_mmu"; 585 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 586 clock-names = "aclk", "iface"; 587 iommu-cells = <0>; 588 status = "disabled"; 589 }; 590 591 sdmmc: dwmmc@30000000 { 592 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 593 reg = <0x30000000 0x4000>; 594 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 596 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 597 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 598 fifo-depth = <0x100>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 601 status = "disabled"; 602 }; 603 604 sdio: dwmmc@30010000 { 605 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 606 reg = <0x30010000 0x4000>; 607 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 609 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 610 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 611 fifo-depth = <0x100>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 614 status = "disabled"; 615 }; 616 617 emmc: dwmmc@30020000 { 618 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 619 reg = <0x30020000 0x4000>; 620 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 621 clock-frequency = <37500000>; 622 max-frequency = <37500000>; 623 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 624 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 625 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 626 bus-width = <8>; 627 default-sample-phase = <158>; 628 fifo-depth = <0x100>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 631 resets = <&cru SRST_EMMC>; 632 reset-names = "reset"; 633 status = "disabled"; 634 }; 635 636 usb_otg: usb@30040000 { 637 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", 638 "snps,dwc2"; 639 reg = <0x30040000 0x40000>; 640 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&cru HCLK_OTG>; 642 clock-names = "otg"; 643 dr_mode = "otg"; 644 g-np-tx-fifo-size = <16>; 645 g-rx-fifo-size = <280>; 646 g-tx-fifo-size = <256 128 128 64 32 16>; 647 g-use-dma; 648 phys = <&u2phy0_otg>; 649 phy-names = "usb2-phy"; 650 status = "disabled"; 651 }; 652 653 usb_host0_ehci: usb@30080000 { 654 compatible = "generic-ehci"; 655 reg = <0x30080000 0x20000>; 656 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 658 clock-names = "usbhost", "utmi"; 659 phys = <&u2phy0_host>; 660 phy-names = "usb"; 661 status = "disabled"; 662 }; 663 664 usb_host0_ohci: usb@300a0000 { 665 compatible = "generic-ohci"; 666 reg = <0x300a0000 0x20000>; 667 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 669 clock-names = "usbhost", "utmi"; 670 phys = <&u2phy0_host>; 671 phy-names = "usb"; 672 status = "disabled"; 673 }; 674 675 usb_host1_ehci: usb@300c0000 { 676 compatible = "generic-ehci"; 677 reg = <0x300c0000 0x20000>; 678 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 680 clock-names = "usbhost", "utmi"; 681 phys = <&u2phy1_otg>; 682 phy-names = "usb"; 683 status = "disabled"; 684 }; 685 686 usb_host1_ohci: usb@300e0000 { 687 compatible = "generic-ohci"; 688 reg = <0x300e0000 0x20000>; 689 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 691 clock-names = "usbhost", "utmi"; 692 phys = <&u2phy1_otg>; 693 phy-names = "usb"; 694 status = "disabled"; 695 }; 696 697 usb_host2_ehci: usb@30100000 { 698 compatible = "generic-ehci"; 699 reg = <0x30100000 0x20000>; 700 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 702 phys = <&u2phy1_host>; 703 phy-names = "usb"; 704 clock-names = "usbhost", "utmi"; 705 status = "disabled"; 706 }; 707 708 usb_host2_ohci: usb@30120000 { 709 compatible = "generic-ohci"; 710 reg = <0x30120000 0x20000>; 711 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 713 clock-names = "usbhost", "utmi"; 714 phys = <&u2phy1_host>; 715 phy-names = "usb"; 716 status = "disabled"; 717 }; 718 719 gmac: ethernet@30200000 { 720 compatible = "rockchip,rk3228-gmac"; 721 reg = <0x30200000 0x10000>; 722 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-names = "macirq"; 724 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 725 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 726 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 727 <&cru PCLK_GMAC>; 728 clock-names = "stmmaceth", "mac_clk_rx", 729 "mac_clk_tx", "clk_mac_ref", 730 "clk_mac_refout", "aclk_mac", 731 "pclk_mac"; 732 resets = <&cru SRST_GMAC>; 733 reset-names = "stmmaceth"; 734 rockchip,grf = <&grf>; 735 status = "disabled"; 736 }; 737 738 gic: interrupt-controller@32010000 { 739 compatible = "arm,gic-400"; 740 interrupt-controller; 741 #interrupt-cells = <3>; 742 #address-cells = <0>; 743 744 reg = <0x32011000 0x1000>, 745 <0x32012000 0x2000>, 746 <0x32014000 0x2000>, 747 <0x32016000 0x2000>; 748 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 749 }; 750 751 pinctrl: pinctrl { 752 compatible = "rockchip,rk3228-pinctrl"; 753 rockchip,grf = <&grf>; 754 #address-cells = <1>; 755 #size-cells = <1>; 756 ranges; 757 758 gpio0: gpio0@11110000 { 759 compatible = "rockchip,gpio-bank"; 760 reg = <0x11110000 0x100>; 761 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&cru PCLK_GPIO0>; 763 764 gpio-controller; 765 #gpio-cells = <2>; 766 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 gpio1: gpio1@11120000 { 772 compatible = "rockchip,gpio-bank"; 773 reg = <0x11120000 0x100>; 774 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cru PCLK_GPIO1>; 776 777 gpio-controller; 778 #gpio-cells = <2>; 779 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 }; 783 784 gpio2: gpio2@11130000 { 785 compatible = "rockchip,gpio-bank"; 786 reg = <0x11130000 0x100>; 787 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cru PCLK_GPIO2>; 789 790 gpio-controller; 791 #gpio-cells = <2>; 792 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 797 gpio3: gpio3@11140000 { 798 compatible = "rockchip,gpio-bank"; 799 reg = <0x11140000 0x100>; 800 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cru PCLK_GPIO3>; 802 803 gpio-controller; 804 #gpio-cells = <2>; 805 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 810 pcfg_pull_up: pcfg-pull-up { 811 bias-pull-up; 812 }; 813 814 pcfg_pull_down: pcfg-pull-down { 815 bias-pull-down; 816 }; 817 818 pcfg_pull_none: pcfg-pull-none { 819 bias-disable; 820 }; 821 822 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 823 drive-strength = <12>; 824 }; 825 826 sdmmc { 827 sdmmc_clk: sdmmc-clk { 828 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 829 }; 830 831 sdmmc_cmd: sdmmc-cmd { 832 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 833 }; 834 835 sdmmc_bus4: sdmmc-bus4 { 836 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 837 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 838 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 839 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 840 }; 841 }; 842 843 sdio { 844 sdio_clk: sdio-clk { 845 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 846 }; 847 848 sdio_cmd: sdio-cmd { 849 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 850 }; 851 852 sdio_bus4: sdio-bus4 { 853 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 854 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 855 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 856 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 857 }; 858 }; 859 860 emmc { 861 emmc_clk: emmc-clk { 862 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 863 }; 864 865 emmc_cmd: emmc-cmd { 866 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; 867 }; 868 869 emmc_bus8: emmc-bus8 { 870 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 871 <1 25 RK_FUNC_2 &pcfg_pull_none>, 872 <1 26 RK_FUNC_2 &pcfg_pull_none>, 873 <1 27 RK_FUNC_2 &pcfg_pull_none>, 874 <1 28 RK_FUNC_2 &pcfg_pull_none>, 875 <1 29 RK_FUNC_2 &pcfg_pull_none>, 876 <1 30 RK_FUNC_2 &pcfg_pull_none>, 877 <1 31 RK_FUNC_2 &pcfg_pull_none>; 878 }; 879 }; 880 881 gmac { 882 rgmii_pins: rgmii-pins { 883 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, 884 <2 12 RK_FUNC_1 &pcfg_pull_none>, 885 <2 25 RK_FUNC_1 &pcfg_pull_none>, 886 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 887 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 888 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 889 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 890 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 891 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 892 <2 17 RK_FUNC_1 &pcfg_pull_none>, 893 <2 16 RK_FUNC_1 &pcfg_pull_none>, 894 <2 21 RK_FUNC_2 &pcfg_pull_none>, 895 <2 20 RK_FUNC_2 &pcfg_pull_none>, 896 <2 11 RK_FUNC_1 &pcfg_pull_none>, 897 <2 8 RK_FUNC_1 &pcfg_pull_none>; 898 }; 899 900 rmii_pins: rmii-pins { 901 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, 902 <2 12 RK_FUNC_1 &pcfg_pull_none>, 903 <2 25 RK_FUNC_1 &pcfg_pull_none>, 904 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 905 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 906 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 907 <2 17 RK_FUNC_1 &pcfg_pull_none>, 908 <2 16 RK_FUNC_1 &pcfg_pull_none>, 909 <2 8 RK_FUNC_1 &pcfg_pull_none>, 910 <2 15 RK_FUNC_1 &pcfg_pull_none>; 911 }; 912 913 phy_pins: phy-pins { 914 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, 915 <2 8 RK_FUNC_2 &pcfg_pull_none>; 916 }; 917 }; 918 919 i2c0 { 920 i2c0_xfer: i2c0-xfer { 921 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 922 <0 1 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 }; 925 926 i2c1 { 927 i2c1_xfer: i2c1-xfer { 928 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 929 <0 3 RK_FUNC_1 &pcfg_pull_none>; 930 }; 931 }; 932 933 i2c2 { 934 i2c2_xfer: i2c2-xfer { 935 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, 936 <2 21 RK_FUNC_1 &pcfg_pull_none>; 937 }; 938 }; 939 940 i2c3 { 941 i2c3_xfer: i2c3-xfer { 942 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 943 <0 7 RK_FUNC_1 &pcfg_pull_none>; 944 }; 945 }; 946 947 spi-0 { 948 spi0_clk: spi0-clk { 949 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; 950 }; 951 spi0_cs0: spi0-cs0 { 952 rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; 953 }; 954 spi0_tx: spi0-tx { 955 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 956 }; 957 spi0_rx: spi0-rx { 958 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 959 }; 960 spi0_cs1: spi0-cs1 { 961 rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; 962 }; 963 }; 964 965 spi-1 { 966 spi1_clk: spi1-clk { 967 rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; 968 }; 969 spi1_cs0: spi1-cs0 { 970 rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; 971 }; 972 spi1_rx: spi1-rx { 973 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; 974 }; 975 spi1_tx: spi1-tx { 976 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; 977 }; 978 spi1_cs1: spi1-cs1 { 979 rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; 980 }; 981 }; 982 983 i2s1 { 984 i2s1_bus: i2s1-bus { 985 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, 986 <0 9 RK_FUNC_1 &pcfg_pull_none>, 987 <0 11 RK_FUNC_1 &pcfg_pull_none>, 988 <0 12 RK_FUNC_1 &pcfg_pull_none>, 989 <0 13 RK_FUNC_1 &pcfg_pull_none>, 990 <0 14 RK_FUNC_1 &pcfg_pull_none>, 991 <1 2 RK_FUNC_2 &pcfg_pull_none>, 992 <1 4 RK_FUNC_2 &pcfg_pull_none>, 993 <1 5 RK_FUNC_2 &pcfg_pull_none>; 994 }; 995 }; 996 997 pwm0 { 998 pwm0_pin: pwm0-pin { 999 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; 1000 }; 1001 }; 1002 1003 pwm1 { 1004 pwm1_pin: pwm1-pin { 1005 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; 1006 }; 1007 }; 1008 1009 pwm2 { 1010 pwm2_pin: pwm2-pin { 1011 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; 1012 }; 1013 }; 1014 1015 pwm3 { 1016 pwm3_pin: pwm3-pin { 1017 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; 1018 }; 1019 }; 1020 1021 spdif { 1022 spdif_tx: spdif-tx { 1023 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; 1024 }; 1025 }; 1026 1027 tsadc { 1028 otp_gpio: otp-gpio { 1029 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; 1030 }; 1031 1032 otp_out: otp-out { 1033 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; 1034 }; 1035 }; 1036 1037 uart0 { 1038 uart0_xfer: uart0-xfer { 1039 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, 1040 <2 27 RK_FUNC_1 &pcfg_pull_none>; 1041 }; 1042 1043 uart0_cts: uart0-cts { 1044 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; 1045 }; 1046 1047 uart0_rts: uart0-rts { 1048 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; 1049 }; 1050 }; 1051 1052 uart1 { 1053 uart1_xfer: uart1-xfer { 1054 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, 1055 <1 10 RK_FUNC_1 &pcfg_pull_none>; 1056 }; 1057 1058 uart1_cts: uart1-cts { 1059 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; 1060 }; 1061 1062 uart1_rts: uart1-rts { 1063 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; 1064 }; 1065 }; 1066 1067 uart2 { 1068 uart2_xfer: uart2-xfer { 1069 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 1070 <1 19 RK_FUNC_2 &pcfg_pull_none>; 1071 }; 1072 1073 uart21_xfer: uart21-xfer { 1074 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, 1075 <1 9 RK_FUNC_2 &pcfg_pull_none>; 1076 }; 1077 1078 uart2_cts: uart2-cts { 1079 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; 1080 }; 1081 1082 uart2_rts: uart2-rts { 1083 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; 1084 }; 1085 }; 1086 }; 1087}; 1088
