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/Linux-v4.19/net/l3mdev/
DKconfig2 # Configuration for L3 master device support
6 bool "L3 Master device support"
10 drivers to support L3 master devices like VRF.
/Linux-v4.19/Documentation/networking/
Dipvlan.txt9 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
32 L3 bridge mode
43 IPvlan has two modes of operation - L2 and L3. For a given master device,
46 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
47 L3 mode is more restrictive since routing is controlled from the other (mostly)
56 4.2 L3 mode:
57 In this mode TX processing up to L3 happens on the stack instance attached
64 This is very similar to the L3 mode except that iptables (conn-tracking)
65 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
66 performance but that shouldn't matter since you are choosing this mode over plain-L3
/Linux-v4.19/drivers/perf/
DKconfig60 Unit (DSU). The DSU integrates one or more cores with an L3 memory
81 bool "Qualcomm Technologies L3-cache PMU"
85 Provides support for the L3 cache performance monitor unit (PMU)
87 Adds the L3 cache PMU into the perf events subsystem for
88 monitoring L3 cache events.
/Linux-v4.19/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/Linux-v4.19/arch/riscv/lib/
Dudivdi3.S29 .L3: label
36 bnez a3, .L3
/Linux-v4.19/Documentation/perf/
Dqcom_l3_pmu.txt1 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
4 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
5 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
Darm_dsu_pmu.txt4 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
6 allows counting the various events related to the L3 cache, Snoop Control Unit
Dxgene-pmu.txt5 L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
24 performance of a specific datapath. For example, agents of a L3 cache can be
/Linux-v4.19/Documentation/devicetree/bindings/sound/
Domap-mcpdm.txt7 <L3 interconnect address, size>;
16 <0x49032000 0x7f>; /* L3 Interconnect */
Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
/Linux-v4.19/arch/x86/events/intel/
Dds.c62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
[all …]
/Linux-v4.19/Documentation/x86/
Dintel_rdt_ui.txt24 "cdp": Enable code/data prioritization in L3 cache allocations.
29 L2 and L3 CDP are controlled seperately.
53 Cache resource(L3/L2) subdirectory contains the following files
135 # echo L3:0=f7 > schemata
214 This contains a set of files organized by L3 domain and by
215 RDT event. E.g. on a system with two L3 domains there will
297 On current generation systems there is one L3 cache per socket and L2
299 isn't an architectural requirement. We could have multiple separate L3
345 This can occur when aggregate L2 external bandwidth is more than L3
348 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/arm/omap/
Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/Linux-v4.19/Documentation/devicetree/bindings/arm/uniphier/
Dcache-uniphier.txt17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
38 Example 2 (system with L2 and L3):
/Linux-v4.19/arch/m68k/lib/
Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/Linux-v4.19/Documentation/translations/zh_CN/arm64/
Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/Linux-v4.19/arch/alpha/kernel/
Dsetup.c1357 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1368 L3 = -1; in determine_cpu_caches()
1389 L3 = -1; in determine_cpu_caches()
1420 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1434 L3 = -1; in determine_cpu_caches()
1457 L3 = -1; in determine_cpu_caches()
1464 L3 = -1; in determine_cpu_caches()
1469 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1476 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/Linux-v4.19/arch/arm/boot/dts/
Domap4.dtsi237 <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
249 <0x49032000 0x7f>; /* L3 Interconnect */
262 <0x4902e000 0x7f>; /* L3 Interconnect */
274 <0x49022000 0xff>; /* L3 Interconnect */
289 <0x49024000 0xff>; /* L3 Interconnect */
304 <0x49026000 0xff>; /* L3 Interconnect */
331 <0x49028000 0x49028000 0x1000>; /* L3 */
357 <0x4902c000 0x4902c000 0x1000>; /* L3 */
380 <0x490f1000 0x490f1000 0x1000>; /* L3 */
Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
/Linux-v4.19/drivers/cpufreq/
Ds5pv210-cpufreq.c113 L0, L1, L2, L3, L4, enumerator
131 {0, L3, 200*1000},
160 [L3] = {
370 if (index >= L3) in s5pv210_target()
/Linux-v4.19/arch/sparc/net/
Dbpf_jit_64.h23 #define L3 0x13 macro
/Linux-v4.19/Documentation/locking/
Drt-mutex-design.txt129 Mutexes: L1, L2, L3, L4
135 C owns L3
136 D blocked on L3
142 E->L4->D->L3->C->L2->B->L1->A
156 E->L4->D->L3->C->L2-+
175 E->L4->D->L3->C-+
220 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
221 The following shows a locking order of L1->L2->L3, but may not actually
247 mutex_lock(L3);
251 mutex_unlock(L3);
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/Linux-v4.19/arch/xtensa/lib/
Dmemset.S83 bbci.l a4, 2, .L3
87 .L3: label
/Linux-v4.19/net/switchdev/
DKconfig11 meaning of the word "switch". This include devices supporting L2/L3 but

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