1Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
2===========================================================================
3
4This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
5Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
6by all cores within a socket. Each slice is exposed as a separate uncore perf
7PMU with device name l3cache_<socket>_<instance>. User space is responsible
8for aggregating across slices.
9
10The driver provides a description of its available events and configuration
11options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
12the driver also exposes a "cpumask" sysfs attribute which contains a mask
13consisting of one CPU per socket which will be used to handle all the PMU
14events on that socket.
15
16The hardware implements 32bit event counters and has a flat 8bit event space
17exposed via the "event" format attribute. In addition to the 32bit physical
18counters the driver supports virtual 64bit hardware counters by using hardware
19counter chaining. This feature is exposed via the "lc" (long counter) format
20flag. E.g.:
21
22  perf stat -e l3cache_0_0/read-miss,lc/
23
24Given that these are uncore PMUs the driver does not support sampling, therefore
25"perf record" will not work. Per-task perf sessions are not supported.
26