1/* 2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/bus/ti-sysc.h> 10#include <dt-bindings/clock/omap4.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/omap.h> 14#include <dt-bindings/clock/omap4.h> 15 16/ { 17 compatible = "ti,omap4430", "ti,omap4"; 18 interrupt-parent = <&wakeupgen>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 serial0 = &uart1; 29 serial1 = &uart2; 30 serial2 = &uart3; 31 serial3 = &uart4; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,cortex-a9"; 40 device_type = "cpu"; 41 next-level-cache = <&L2>; 42 reg = <0x0>; 43 44 clocks = <&dpll_mpu_ck>; 45 clock-names = "cpu"; 46 47 clock-latency = <300000>; /* From omap-cpufreq driver */ 48 }; 49 cpu@1 { 50 compatible = "arm,cortex-a9"; 51 device_type = "cpu"; 52 next-level-cache = <&L2>; 53 reg = <0x1>; 54 }; 55 }; 56 57 /* 58 * Note that 4430 needs cross trigger interface (CTI) supported 59 * before we can configure the interrupts. This means sampling 60 * events are not supported for pmu. Note that 4460 does not use 61 * CTI, see also 4460.dtsi. 62 */ 63 pmu { 64 compatible = "arm,cortex-a9-pmu"; 65 ti,hwmods = "debugss"; 66 }; 67 68 gic: interrupt-controller@48241000 { 69 compatible = "arm,cortex-a9-gic"; 70 interrupt-controller; 71 #interrupt-cells = <3>; 72 reg = <0x48241000 0x1000>, 73 <0x48240100 0x0100>; 74 interrupt-parent = <&gic>; 75 }; 76 77 L2: l2-cache-controller@48242000 { 78 compatible = "arm,pl310-cache"; 79 reg = <0x48242000 0x1000>; 80 cache-unified; 81 cache-level = <2>; 82 }; 83 84 local-timer@48240600 { 85 compatible = "arm,cortex-a9-twd-timer"; 86 clocks = <&mpu_periphclk>; 87 reg = <0x48240600 0x20>; 88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; 89 interrupt-parent = <&gic>; 90 }; 91 92 wakeupgen: interrupt-controller@48281000 { 93 compatible = "ti,omap4-wugen-mpu"; 94 interrupt-controller; 95 #interrupt-cells = <3>; 96 reg = <0x48281000 0x1000>; 97 interrupt-parent = <&gic>; 98 }; 99 100 /* 101 * The soc node represents the soc top level view. It is used for IPs 102 * that are not memory mapped in the MPU view or for the MPU itself. 103 */ 104 soc { 105 compatible = "ti,omap-infra"; 106 mpu { 107 compatible = "ti,omap4-mpu"; 108 ti,hwmods = "mpu"; 109 sram = <&ocmcram>; 110 }; 111 112 dsp { 113 compatible = "ti,omap3-c64"; 114 ti,hwmods = "dsp"; 115 }; 116 117 iva { 118 compatible = "ti,ivahd"; 119 ti,hwmods = "iva"; 120 }; 121 }; 122 123 /* 124 * XXX: Use a flat representation of the OMAP4 interconnect. 125 * The real OMAP interconnect network is quite complex. 126 * Since it will not bring real advantage to represent that in DT for 127 * the moment, just use a fake OCP bus entry to represent the whole bus 128 * hierarchy. 129 */ 130 ocp { 131 compatible = "ti,omap4-l3-noc", "simple-bus"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 136 reg = <0x44000000 0x1000>, 137 <0x44800000 0x2000>, 138 <0x45000000 0x1000>; 139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 141 142 l4_wkup: interconnect@4a300000 { 143 }; 144 145 l4_cfg: interconnect@4a000000 { 146 }; 147 148 l4_per: interconnect@48000000 { 149 }; 150 151 ocmcram: ocmcram@40304000 { 152 compatible = "mmio-sram"; 153 reg = <0x40304000 0xa000>; /* 40k */ 154 }; 155 156 gpmc: gpmc@50000000 { 157 compatible = "ti,omap4430-gpmc"; 158 reg = <0x50000000 0x1000>; 159 #address-cells = <2>; 160 #size-cells = <1>; 161 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 162 dmas = <&sdma 4>; 163 dma-names = "rxtx"; 164 gpmc,num-cs = <8>; 165 gpmc,num-waitpins = <4>; 166 ti,hwmods = "gpmc"; 167 ti,no-idle-on-init; 168 clocks = <&l3_div_ck>; 169 clock-names = "fck"; 170 interrupt-controller; 171 #interrupt-cells = <2>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 }; 175 176 mmu_dsp: mmu@4a066000 { 177 compatible = "ti,omap4-iommu"; 178 reg = <0x4a066000 0x100>; 179 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 180 ti,hwmods = "mmu_dsp"; 181 #iommu-cells = <0>; 182 }; 183 184 target-module@52000000 { 185 compatible = "ti,sysc-omap4", "ti,sysc"; 186 ti,hwmods = "iss"; 187 reg = <0x52000000 0x4>, 188 <0x52000010 0x4>; 189 reg-names = "rev", "sysc"; 190 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 191 ti,sysc-midle = <SYSC_IDLE_FORCE>, 192 <SYSC_IDLE_NO>, 193 <SYSC_IDLE_SMART>, 194 <SYSC_IDLE_SMART_WKUP>; 195 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 196 <SYSC_IDLE_NO>, 197 <SYSC_IDLE_SMART>, 198 <SYSC_IDLE_SMART_WKUP>; 199 ti,sysc-delay-us = <2>; 200 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; 201 clock-names = "fck"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges = <0 0x52000000 0x1000000>; 205 206 /* No child device binding, driver in staging */ 207 }; 208 209 mmu_ipu: mmu@55082000 { 210 compatible = "ti,omap4-iommu"; 211 reg = <0x55082000 0x100>; 212 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 213 ti,hwmods = "mmu_ipu"; 214 #iommu-cells = <0>; 215 ti,iommu-bus-err-back; 216 }; 217 target-module@40130000 { 218 compatible = "ti,sysc-omap2", "ti,sysc"; 219 ti,hwmods = "wd_timer3"; 220 reg = <0x40130000 0x4>, 221 <0x40130010 0x4>, 222 <0x40130014 0x4>; 223 reg-names = "rev", "sysc", "syss"; 224 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 225 SYSC_OMAP2_SOFTRESET)>; 226 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 227 <SYSC_IDLE_NO>, 228 <SYSC_IDLE_SMART>, 229 <SYSC_IDLE_SMART_WKUP>; 230 ti,syss-mask = <1>; 231 /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ 232 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; 233 clock-names = "fck"; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ 237 <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ 238 239 wdt3: wdt@0 { 240 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 241 reg = <0x0 0x80>; 242 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 243 }; 244 }; 245 246 mcpdm: mcpdm@40132000 { 247 compatible = "ti,omap4-mcpdm"; 248 reg = <0x40132000 0x7f>, /* MPU private access */ 249 <0x49032000 0x7f>; /* L3 Interconnect */ 250 reg-names = "mpu", "dma"; 251 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 252 ti,hwmods = "mcpdm"; 253 dmas = <&sdma 65>, 254 <&sdma 66>; 255 dma-names = "up_link", "dn_link"; 256 status = "disabled"; 257 }; 258 259 dmic: dmic@4012e000 { 260 compatible = "ti,omap4-dmic"; 261 reg = <0x4012e000 0x7f>, /* MPU private access */ 262 <0x4902e000 0x7f>; /* L3 Interconnect */ 263 reg-names = "mpu", "dma"; 264 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 265 ti,hwmods = "dmic"; 266 dmas = <&sdma 67>; 267 dma-names = "up_link"; 268 status = "disabled"; 269 }; 270 271 mcbsp1: mcbsp@40122000 { 272 compatible = "ti,omap4-mcbsp"; 273 reg = <0x40122000 0xff>, /* MPU private access */ 274 <0x49022000 0xff>; /* L3 Interconnect */ 275 reg-names = "mpu", "dma"; 276 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "common"; 278 ti,buffer-size = <128>; 279 ti,hwmods = "mcbsp1"; 280 dmas = <&sdma 33>, 281 <&sdma 34>; 282 dma-names = "tx", "rx"; 283 status = "disabled"; 284 }; 285 286 mcbsp2: mcbsp@40124000 { 287 compatible = "ti,omap4-mcbsp"; 288 reg = <0x40124000 0xff>, /* MPU private access */ 289 <0x49024000 0xff>; /* L3 Interconnect */ 290 reg-names = "mpu", "dma"; 291 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "common"; 293 ti,buffer-size = <128>; 294 ti,hwmods = "mcbsp2"; 295 dmas = <&sdma 17>, 296 <&sdma 18>; 297 dma-names = "tx", "rx"; 298 status = "disabled"; 299 }; 300 301 mcbsp3: mcbsp@40126000 { 302 compatible = "ti,omap4-mcbsp"; 303 reg = <0x40126000 0xff>, /* MPU private access */ 304 <0x49026000 0xff>; /* L3 Interconnect */ 305 reg-names = "mpu", "dma"; 306 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "common"; 308 ti,buffer-size = <128>; 309 ti,hwmods = "mcbsp3"; 310 dmas = <&sdma 19>, 311 <&sdma 20>; 312 dma-names = "tx", "rx"; 313 status = "disabled"; 314 }; 315 316 target-module@40128000 { 317 compatible = "ti,sysc-mcasp", "ti,sysc"; 318 ti,hwmods = "mcasp"; 319 reg = <0x40128000 0x4>, 320 <0x40128004 0x4>; 321 reg-names = "rev", "sysc"; 322 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 323 <SYSC_IDLE_NO>, 324 <SYSC_IDLE_SMART>, 325 <SYSC_IDLE_SMART_WKUP>; 326 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; 327 clock-names = "fck"; 328 #address-cells = <1>; 329 #size-cells = <1>; 330 ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ 331 <0x49028000 0x49028000 0x1000>; /* L3 */ 332 333 /* 334 * Child device unsupported by davinci-mcasp. At least 335 * RX path is disabled for omap4, and only DIT mode 336 * works with no I2S. See also old Android kernel 337 * omap-mcasp driver for more information. 338 */ 339 }; 340 341 target-module@4012c000 { 342 compatible = "ti,sysc-omap4", "ti,sysc"; 343 ti,hwmods = "slimbus1"; 344 reg = <0x4012c000 0x4>, 345 <0x4012c010 0x4>; 346 reg-names = "rev", "sysc"; 347 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 348 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 349 <SYSC_IDLE_NO>, 350 <SYSC_IDLE_SMART>, 351 <SYSC_IDLE_SMART_WKUP>; 352 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; 353 clock-names = "fck"; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ 357 <0x4902c000 0x4902c000 0x1000>; /* L3 */ 358 359 /* No child device binding or driver in mainline */ 360 }; 361 362 target-module@401f1000 { 363 compatible = "ti,sysc-omap4", "ti,sysc"; 364 ti,hwmods = "aess"; 365 reg = <0x401f1000 0x4>, 366 <0x401f1010 0x4>; 367 reg-names = "rev", "sysc"; 368 ti,sysc-midle = <SYSC_IDLE_FORCE>, 369 <SYSC_IDLE_NO>, 370 <SYSC_IDLE_SMART>, 371 <SYSC_IDLE_SMART_WKUP>; 372 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 373 <SYSC_IDLE_NO>, 374 <SYSC_IDLE_SMART>; 375 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; 376 clock-names = "fck"; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ 380 <0x490f1000 0x490f1000 0x1000>; /* L3 */ 381 382 /* 383 * No child device binding or driver in mainline. 384 * See Android tree and related upstreaming efforts 385 * for the old driver. 386 */ 387 }; 388 389 dmm@4e000000 { 390 compatible = "ti,omap4-dmm"; 391 reg = <0x4e000000 0x800>; 392 interrupts = <0 113 0x4>; 393 ti,hwmods = "dmm"; 394 }; 395 396 emif1: emif@4c000000 { 397 compatible = "ti,emif-4d"; 398 reg = <0x4c000000 0x100>; 399 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 400 ti,hwmods = "emif1"; 401 ti,no-idle-on-init; 402 phy-type = <1>; 403 hw-caps-read-idle-ctrl; 404 hw-caps-ll-interface; 405 hw-caps-temp-alert; 406 }; 407 408 emif2: emif@4d000000 { 409 compatible = "ti,emif-4d"; 410 reg = <0x4d000000 0x100>; 411 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 412 ti,hwmods = "emif2"; 413 ti,no-idle-on-init; 414 phy-type = <1>; 415 hw-caps-read-idle-ctrl; 416 hw-caps-ll-interface; 417 hw-caps-temp-alert; 418 }; 419 420 timer5: timer@40138000 { 421 compatible = "ti,omap4430-timer"; 422 reg = <0x40138000 0x80>, 423 <0x49038000 0x80>; 424 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 425 ti,hwmods = "timer5"; 426 ti,timer-dsp; 427 }; 428 429 timer6: timer@4013a000 { 430 compatible = "ti,omap4430-timer"; 431 reg = <0x4013a000 0x80>, 432 <0x4903a000 0x80>; 433 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 434 ti,hwmods = "timer6"; 435 ti,timer-dsp; 436 }; 437 438 timer7: timer@4013c000 { 439 compatible = "ti,omap4430-timer"; 440 reg = <0x4013c000 0x80>, 441 <0x4903c000 0x80>; 442 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 443 ti,hwmods = "timer7"; 444 ti,timer-dsp; 445 }; 446 447 timer8: timer@4013e000 { 448 compatible = "ti,omap4430-timer"; 449 reg = <0x4013e000 0x80>, 450 <0x4903e000 0x80>; 451 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 452 ti,hwmods = "timer8"; 453 ti,timer-pwm; 454 ti,timer-dsp; 455 }; 456 457 aes1: aes@4b501000 { 458 compatible = "ti,omap4-aes"; 459 ti,hwmods = "aes1"; 460 reg = <0x4b501000 0xa0>; 461 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 462 dmas = <&sdma 111>, <&sdma 110>; 463 dma-names = "tx", "rx"; 464 }; 465 466 aes2: aes@4b701000 { 467 compatible = "ti,omap4-aes"; 468 ti,hwmods = "aes2"; 469 reg = <0x4b701000 0xa0>; 470 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 471 dmas = <&sdma 114>, <&sdma 113>; 472 dma-names = "tx", "rx"; 473 }; 474 475 des: des@480a5000 { 476 compatible = "ti,omap4-des"; 477 ti,hwmods = "des"; 478 reg = <0x480a5000 0xa0>; 479 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 480 dmas = <&sdma 117>, <&sdma 116>; 481 dma-names = "tx", "rx"; 482 }; 483 484 sham: sham@4b100000 { 485 compatible = "ti,omap4-sham"; 486 ti,hwmods = "sham"; 487 reg = <0x4b100000 0x300>; 488 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 489 dmas = <&sdma 119>; 490 dma-names = "rx"; 491 }; 492 493 abb_mpu: regulator-abb-mpu { 494 compatible = "ti,abb-v2"; 495 regulator-name = "abb_mpu"; 496 #address-cells = <0>; 497 #size-cells = <0>; 498 ti,tranxdone-status-mask = <0x80>; 499 clocks = <&sys_clkin_ck>; 500 ti,settling-time = <50>; 501 ti,clock-cycles = <16>; 502 503 status = "disabled"; 504 }; 505 506 abb_iva: regulator-abb-iva { 507 compatible = "ti,abb-v2"; 508 regulator-name = "abb_iva"; 509 #address-cells = <0>; 510 #size-cells = <0>; 511 ti,tranxdone-status-mask = <0x80000000>; 512 clocks = <&sys_clkin_ck>; 513 ti,settling-time = <50>; 514 ti,clock-cycles = <16>; 515 516 status = "disabled"; 517 }; 518 519 target-module@56000000 { 520 compatible = "ti,sysc-omap4", "ti,sysc"; 521 ti,hwmods = "gpu"; 522 reg = <0x5601fc00 0x4>, 523 <0x5601fc10 0x4>; 524 reg-names = "rev", "sysc"; 525 ti,sysc-midle = <SYSC_IDLE_FORCE>, 526 <SYSC_IDLE_NO>, 527 <SYSC_IDLE_SMART>, 528 <SYSC_IDLE_SMART_WKUP>; 529 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 530 <SYSC_IDLE_NO>, 531 <SYSC_IDLE_SMART>, 532 <SYSC_IDLE_SMART_WKUP>; 533 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; 534 clock-names = "fck"; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 ranges = <0 0x56000000 0x2000000>; 538 539 /* 540 * Closed source PowerVR driver, no child device 541 * binding or driver in mainline 542 */ 543 }; 544 545 dss: dss@58000000 { 546 compatible = "ti,omap4-dss"; 547 reg = <0x58000000 0x80>; 548 status = "disabled"; 549 ti,hwmods = "dss_core"; 550 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; 551 clock-names = "fck"; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 ranges; 555 556 dispc@58001000 { 557 compatible = "ti,omap4-dispc"; 558 reg = <0x58001000 0x1000>; 559 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 560 ti,hwmods = "dss_dispc"; 561 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; 562 clock-names = "fck"; 563 }; 564 565 rfbi: encoder@58002000 { 566 compatible = "ti,omap4-rfbi"; 567 reg = <0x58002000 0x1000>; 568 status = "disabled"; 569 ti,hwmods = "dss_rfbi"; 570 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; 571 clock-names = "fck", "ick"; 572 }; 573 574 venc: encoder@58003000 { 575 compatible = "ti,omap4-venc"; 576 reg = <0x58003000 0x1000>; 577 status = "disabled"; 578 ti,hwmods = "dss_venc"; 579 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; 580 clock-names = "fck"; 581 }; 582 583 dsi1: encoder@58004000 { 584 compatible = "ti,omap4-dsi"; 585 reg = <0x58004000 0x200>, 586 <0x58004200 0x40>, 587 <0x58004300 0x20>; 588 reg-names = "proto", "phy", "pll"; 589 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 590 status = "disabled"; 591 ti,hwmods = "dss_dsi1"; 592 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 593 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 594 clock-names = "fck", "sys_clk"; 595 }; 596 597 dsi2: encoder@58005000 { 598 compatible = "ti,omap4-dsi"; 599 reg = <0x58005000 0x200>, 600 <0x58005200 0x40>, 601 <0x58005300 0x20>; 602 reg-names = "proto", "phy", "pll"; 603 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 604 status = "disabled"; 605 ti,hwmods = "dss_dsi2"; 606 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 607 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 608 clock-names = "fck", "sys_clk"; 609 }; 610 611 hdmi: encoder@58006000 { 612 compatible = "ti,omap4-hdmi"; 613 reg = <0x58006000 0x200>, 614 <0x58006200 0x100>, 615 <0x58006300 0x100>, 616 <0x58006400 0x1000>; 617 reg-names = "wp", "pll", "phy", "core"; 618 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 619 status = "disabled"; 620 ti,hwmods = "dss_hdmi"; 621 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, 622 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 623 clock-names = "fck", "sys_clk"; 624 dmas = <&sdma 76>; 625 dma-names = "audio_tx"; 626 }; 627 }; 628 }; 629}; 630 631#include "omap4-l4.dtsi" 632#include "omap44xx-clocks.dtsi" 633
