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Searched refs:INTEL_GEN (Results 1 – 25 of 65) sorted by relevance

123

/Linux-v4.19/drivers/gpu/drm/i915/
Di915_suspend.c35 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
46 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
73 if (INTEL_GEN(dev_priv) < 7) in i915_save_state()
117 if (INTEL_GEN(dev_priv) < 7) in i915_restore_state()
Dintel_device_info.c651 if (INTEL_GEN(dev_priv) <= 4) { in read_timestamp_frequency()
659 } else if (INTEL_GEN(dev_priv) <= 8) { in read_timestamp_frequency()
667 } else if (INTEL_GEN(dev_priv) <= 9) { in read_timestamp_frequency()
685 } else if (INTEL_GEN(dev_priv) <= 11) { in read_timestamp_frequency()
699 if (INTEL_GEN(dev_priv) <= 10) in read_timestamp_frequency()
744 if (INTEL_GEN(dev_priv) >= 10) { in intel_device_info_runtime_init()
747 } else if (INTEL_GEN(dev_priv) == 9) { in intel_device_info_runtime_init()
774 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { in intel_device_info_runtime_init()
847 else if (INTEL_GEN(dev_priv) == 9) in intel_device_info_runtime_init()
849 else if (INTEL_GEN(dev_priv) == 10) in intel_device_info_runtime_init()
[all …]
Dintel_engine_cs.c198 switch (INTEL_GEN(dev_priv)) { in __intel_engine_context_size()
200 MISSING_CASE(INTEL_GEN(dev_priv)); in __intel_engine_context_size()
236 if (INTEL_GEN(dev_priv) < 8) in __intel_engine_context_size()
248 if (INTEL_GEN(i915) >= bases[i].gen) in __engine_mmio_base()
749 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_active_head()
752 else if (INTEL_GEN(dev_priv) >= 4) in intel_engine_get_active_head()
765 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_last_batch_head()
781 if (INTEL_GEN(dev_priv) < 3) in intel_engine_stop_cs()
821 if (INTEL_GEN(dev_priv) == 10) in intel_calculate_mcr_s_ss_select()
824 else if (INTEL_GEN(dev_priv) >= 11) in intel_calculate_mcr_s_ss_select()
[all …]
Dintel_fbc.c51 return INTEL_GEN(dev_priv) <= 3; in no_fbc_on_multiple_pipes()
87 if (INTEL_GEN(dev_priv) == 7) in intel_fbc_calculate_cfb_size()
89 else if (INTEL_GEN(dev_priv) >= 8) in intel_fbc_calculate_cfb_size()
350 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_is_active()
364 if (INTEL_GEN(dev_priv) >= 7) in intel_fbc_hw_activate()
366 else if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_activate()
380 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_deactivate()
473 if (ret && INTEL_GEN(dev_priv) <= 4) { in find_compression_threshold()
506 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_alloc_cfb()
629 if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { in intel_fbc_hw_tracking_covers_screen()
[all …]
Di915_debugfs.c46 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); in i915_capabilities()
765 } else if (INTEL_GEN(dev_priv) >= 11) { in i915_interrupt_info()
786 } else if (INTEL_GEN(dev_priv) >= 8) { in i915_interrupt_info()
882 if (INTEL_GEN(dev_priv) >= 11) { in i915_interrupt_info()
902 } else if (INTEL_GEN(dev_priv) >= 6) { in i915_interrupt_info()
1114 } else if (INTEL_GEN(dev_priv) >= 6) { in i915_frequency_info()
1138 if (INTEL_GEN(dev_priv) >= 9) in i915_frequency_info()
1165 if (INTEL_GEN(dev_priv) >= 11) { in i915_frequency_info()
1174 } else if (INTEL_GEN(dev_priv) >= 8) { in i915_frequency_info()
1197 if (INTEL_GEN(dev_priv) <= 10) in i915_frequency_info()
[all …]
Dintel_psr.c67 if (INTEL_GEN(dev_priv) >= 8) { in intel_psr_irq_control()
130 if (INTEL_GEN(dev_priv) >= 8) in intel_psr_irq_handler()
152 if (INTEL_GEN(dev_priv) >= 9) { in intel_psr_irq_handler()
216 if (INTEL_GEN(dev_priv) >= 9 && in intel_psr_init_dpcd()
326 if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) in intel_psr_enable_sink()
383 if (INTEL_GEN(dev_priv) >= 8) in hsw_activate_psr1()
409 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in hsw_activate_psr2()
444 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { in intel_psr2_config_valid()
529 if (INTEL_GEN(dev_priv) >= 9) in intel_psr_activate()
561 if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) in intel_psr_enable_source()
Di915_gem_tiling.c83 if (INTEL_GEN(i915) >= 4) { in i915_gem_fence_size()
123 if (INTEL_GEN(i915) >= 4) in i915_gem_fence_alignment()
151 if (INTEL_GEN(i915) >= 7) { in i915_tiling_ok()
154 } else if (INTEL_GEN(i915) >= 4) { in i915_tiling_ok()
Dintel_workarounds.c520 if (INTEL_GEN(dev_priv) < 8) in intel_ctx_workarounds_init()
541 MISSING_CASE(INTEL_GEN(dev_priv)); in intel_ctx_workarounds_init()
752 if (INTEL_GEN(dev_priv) >= 10 && in wa_init_mcr()
775 if (INTEL_GEN(dev_priv) >= 11) in wa_init_mcr()
912 if (INTEL_GEN(dev_priv) < 8) in intel_gt_workarounds_apply()
933 MISSING_CASE(INTEL_GEN(dev_priv)); in intel_gt_workarounds_apply()
1024 if (INTEL_GEN(i915) < 8) in whitelist_build()
1045 MISSING_CASE(INTEL_GEN(i915)); in whitelist_build()
Di915_gpu_error.c414 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) in error_print_instdone()
420 if (INTEL_GEN(m->i915) <= 6) in error_print_instdone()
495 if (INTEL_GEN(m->i915) >= 4) { in error_print_engine()
504 if (INTEL_GEN(m->i915) >= 6) { in error_print_engine()
518 if (INTEL_GEN(m->i915) >= 8) { in error_print_engine()
713 if (INTEL_GEN(dev_priv) >= 6) { in i915_error_state_to_str()
716 if (INTEL_GEN(dev_priv) >= 8) in i915_error_state_to_str()
1110 if (INTEL_GEN(dev_priv) >= 6) { in gem_record_fences()
1113 } else if (INTEL_GEN(dev_priv) >= 4) { in gem_record_fences()
1194 if (INTEL_GEN(dev_priv) >= 6) { in error_record_engine_registers()
[all …]
Di915_irq.c362 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11); in gen6_pm_iir()
364 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
369 if (INTEL_GEN(dev_priv) >= 11) in gen6_pm_imr()
371 else if (INTEL_GEN(dev_priv) >= 8) in gen6_pm_imr()
379 if (INTEL_GEN(dev_priv) >= 11) in gen6_pm_ier()
381 else if (INTEL_GEN(dev_priv) >= 8) in gen6_pm_ier()
496 if (INTEL_GEN(dev_priv) >= 11) in gen6_enable_rps_interrupts()
530 if (INTEL_GEN(dev_priv) >= 11) in gen6_disable_rps_interrupts()
671 if (INTEL_GEN(dev_priv) < 5) in i915_pipestat_enable_mask()
762 if (INTEL_GEN(dev_priv) >= 4) in i915_enable_asle_pipestat()
[all …]
Dintel_sprite.c264 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in skl_update_plane()
967 int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384; in intel_check_sprite_plane()
991 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane()
1059 if (INTEL_GEN(dev_priv) < 9 && ( in intel_check_sprite_plane()
1070 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane()
1082 } else if (INTEL_GEN(dev_priv) >= 7) { in intel_check_sprite_plane()
1096 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in intel_check_sprite_plane()
1104 return INTEL_GEN(dev_priv) >= 9; in has_dst_key_in_primary_plane()
1128 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
1167 if (INTEL_GEN(dev_priv) >= 9 && in intel_sprite_set_colorkey_ioctl()
[all …]
Dintel_ringbuffer.c350 if (INTEL_GEN(dev_priv) >= 4) in ring_setup_phys_status_page()
390 if (INTEL_GEN(dev_priv) >= 6) { in intel_ring_setup_status_page()
428 if (INTEL_GEN(dev_priv) > 2) { in stop_ring()
537 if (INTEL_GEN(dev_priv) > 2) in init_ring_common()
662 if (INTEL_GEN(dev_priv) >= 6) in init_render_ring()
1458 WARN_ON(INTEL_GEN(dev_priv) > 2 && in intel_engine_cleanup()
2069 GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); in intel_ring_init_semaphores()
2124 if (INTEL_GEN(dev_priv) >= 6) { in intel_ring_init_irq()
2128 } else if (INTEL_GEN(dev_priv) >= 5) { in intel_ring_init_irq()
2132 } else if (INTEL_GEN(dev_priv) >= 3) { in intel_ring_init_irq()
[all …]
Dintel_display.c1090 if (INTEL_GEN(dev_priv) >= 4) { in intel_wait_for_pipe_off()
1547 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_enable_pll()
2034 if (INTEL_GEN(dev_priv) >= 9) in intel_linear_alignment()
2039 else if (INTEL_GEN(dev_priv) >= 4) in intel_linear_alignment()
2058 if (INTEL_GEN(dev_priv) >= 9) in intel_surf_alignment()
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc; in intel_plane_uses_fence()
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) { in intel_pin_and_fence_fb_obj()
3230 if (INTEL_GEN(dev_priv) < 5) in i9xx_plane_ctl()
3260 if (INTEL_GEN(dev_priv) >= 4 && in i9xx_plane_ctl()
3283 if (INTEL_GEN(dev_priv) >= 4) in i9xx_check_plane_surface()
[all …]
Dintel_uncore.c442 if (INTEL_GEN(dev_priv) < 9) in intel_uncore_edram_size()
452 INTEL_GEN(dev_priv) >= 9) { in intel_uncore_edram_detect()
870 (INTEL_GEN(dev_priv) >= 9 || \
1388 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) in intel_uncore_fw_domains_init()
1402 if (INTEL_GEN(dev_priv) >= 11) { in intel_uncore_fw_domains_init()
1606 if (INTEL_GEN(dev_priv) >= 11) { in intel_uncore_prune()
1737 if (INTEL_GEN(dev_priv) < 3) in i915_stop_engines()
2111 if (INTEL_GEN(dev_priv) >= 11) in gen8_reset_engines()
2130 if (INTEL_GEN(dev_priv) >= 8) in intel_get_gpu_reset()
2132 else if (INTEL_GEN(dev_priv) >= 6) in intel_get_gpu_reset()
[all …]
Dintel_pm.c2575 if (INTEL_GEN(dev_priv) >= 8) in ilk_display_fifo_size()
2577 else if (INTEL_GEN(dev_priv) >= 7) in ilk_display_fifo_size()
2587 if (INTEL_GEN(dev_priv) >= 8) in ilk_plane_wm_reg_max()
2590 else if (INTEL_GEN(dev_priv) >= 7) in ilk_plane_wm_reg_max()
2604 if (INTEL_GEN(dev_priv) >= 7) in ilk_cursor_wm_reg_max()
2612 if (INTEL_GEN(dev_priv) >= 8) in ilk_fbc_wm_reg_max()
2641 if (INTEL_GEN(dev_priv) <= 6) in ilk_plane_wm_max()
2802 if (INTEL_GEN(dev_priv) >= 9) { in intel_read_wm_latency()
2887 } else if (INTEL_GEN(dev_priv) >= 6) { in intel_read_wm_latency()
2894 } else if (INTEL_GEN(dev_priv) >= 5) { in intel_read_wm_latency()
[all …]
Di915_gem_stolen.c55 if (INTEL_GEN(dev_priv) >= 8 && start < 4096) in i915_gem_stolen_insert_node_in_range()
98 if (INTEL_GEN(dev_priv) <= 4 && in i915_adjust_stolen()
388 if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { in i915_gem_init_stolen()
408 switch (INTEL_GEN(dev_priv)) { in i915_gem_init_stolen()
Dintel_lvds.c141 if (INTEL_GEN(dev_priv) < 5) in intel_lvds_get_config()
146 if (INTEL_GEN(dev_priv) < 4) { in intel_lvds_get_config()
191 if (INTEL_GEN(dev_priv) <= 4 && in intel_lvds_pps_get_hw_state()
405 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
842 if (INTEL_GEN(dev_priv) <= 4 && in intel_lvds_supported()
Dintel_atomic.c335 if ((INTEL_GEN(dev_priv) >= 9) && in intel_atomic_setup_scalers()
339 if (INTEL_GEN(dev_priv) == 9 && in intel_atomic_setup_scalers()
Dintel_lrc.c242 if (INTEL_GEN(ctx->i915) >= 11) { in intel_lr_context_descriptor_update()
1679 switch (INTEL_GEN(engine->i915)) { in intel_init_workaround_bb()
1695 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_init_workaround_bb()
1748 if (INTEL_GEN(dev_priv) >= 11) in enable_execlists()
2337 if (INTEL_GEN(engine->i915) < 11) { in logical_ring_default_vfuncs()
2356 if (INTEL_GEN(engine->i915) < 11) { in logical_ring_default_irqs()
2460 if (INTEL_GEN(dev_priv) >= 9) in logical_render_ring_init()
2503 if (INTEL_GEN(dev_priv) < 9) in make_rpcs()
2541 switch (INTEL_GEN(engine->i915)) { in intel_lr_indirect_ctx_offset()
2543 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_lr_indirect_ctx_offset()
[all …]
Di915_gem_fence_reg.c67 if (INTEL_GEN(fence->i915) >= 6) { in i965_write_fence_reg()
560 if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) { in i915_gem_detect_bit_6_swizzle()
570 } else if (INTEL_GEN(dev_priv) >= 6) { in i915_gem_detect_bit_6_swizzle()
Di915_gem_gtt.c158 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) in intel_sanitize_enable_ppgtt()
2226 else if (INTEL_GEN(dev_priv) >= 9) in gtt_write_workarounds()
2241 INTEL_GEN(dev_priv) <= 10) in gtt_write_workarounds()
2264 else if (INTEL_GEN(dev_priv) >= 8) in i915_ppgtt_init_hw()
2267 MISSING_CASE(INTEL_GEN(dev_priv)); in i915_ppgtt_init_hw()
2275 if (INTEL_GEN(i915) < 8) in __hw_ppgtt_create()
2412 if (INTEL_GEN(dev_priv) >= 8) in i915_check_and_clear_faults()
2414 else if (INTEL_GEN(dev_priv) >= 6) in i915_check_and_clear_faults()
2427 if (INTEL_GEN(dev_priv) < 6) in i915_gem_suspend_gtt_mappings()
3070 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) in ggtt_probe_common()
[all …]
Di915_drv.c472 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
477 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
504 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
517 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
556 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
971 if (INTEL_GEN(dev_priv) < 5) in i915_mmio_setup()
1177 if (INTEL_GEN(dev_priv) >= 5) { in i915_driver_init_hw()
1670 if (!(hibernation && INTEL_GEN(dev_priv) < 6)) in i915_drm_suspend_late()
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Di915_gem_object.c382 if (INTEL_GEN(i915) <= 2) { in igt_partial_tiling()
397 if (INTEL_GEN(i915) < 4) in igt_partial_tiling()
399 else if (INTEL_GEN(i915) < 7) in igt_partial_tiling()
412 if (pitch > 2 && INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
421 if (pitch < max_pitch && INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
431 if (INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
Di915_gem_coherency.c222 if (INTEL_GEN(i915) >= 8) { in gpu_set()
227 } else if (INTEL_GEN(i915) >= 4) { in gpu_set()
Dintel_uncore.c187 INTEL_GEN(i915) >= 9); in intel_uncore_live_selftests()

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