Lines Matching refs:INTEL_GEN
1090 if (INTEL_GEN(dev_priv) >= 4) { in intel_wait_for_pipe_off()
1547 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_enable_pll()
2034 if (INTEL_GEN(dev_priv) >= 9) in intel_linear_alignment()
2039 else if (INTEL_GEN(dev_priv) >= 4) in intel_linear_alignment()
2058 if (INTEL_GEN(dev_priv) >= 9) in intel_surf_alignment()
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc; in intel_plane_uses_fence()
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) { in intel_pin_and_fence_fb_obj()
3230 if (INTEL_GEN(dev_priv) < 5) in i9xx_plane_ctl()
3260 if (INTEL_GEN(dev_priv) >= 4 && in i9xx_plane_ctl()
3283 if (INTEL_GEN(dev_priv) >= 4) in i9xx_check_plane_surface()
3327 if (INTEL_GEN(dev_priv) >= 4) in i9xx_update_plane()
3334 if (INTEL_GEN(dev_priv) < 4) { in i9xx_update_plane()
3358 } else if (INTEL_GEN(dev_priv) >= 4) { in i9xx_update_plane()
3384 if (INTEL_GEN(dev_priv) >= 4) in i9xx_disable_plane()
3415 if (INTEL_GEN(dev_priv) >= 5) in i9xx_plane_get_hw_state()
3616 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { in skl_plane_ctl()
3634 if (INTEL_GEN(dev_priv) >= 10) in skl_plane_ctl()
3654 if (INTEL_GEN(dev_priv) < 11) { in glk_plane_color_ctl()
3716 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); in gpu_reset_clobbers_display()
3852 if (INTEL_GEN(dev_priv) >= 9) { in intel_update_pipe_config()
4824 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && in skl_update_scaler()
5223 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) || in needs_nv12_wa()
5650 if (INTEL_GEN(dev_priv) >= 11) in haswell_crtc_enable()
5689 if (INTEL_GEN(dev_priv) >= 9) in haswell_crtc_enable()
5704 if (INTEL_GEN(dev_priv) >= 11) { in haswell_crtc_enable()
5718 if (INTEL_GEN(dev_priv) >= 11) in haswell_crtc_enable()
5847 if (INTEL_GEN(dev_priv) >= 9) in haswell_crtc_disable()
5854 if (INTEL_GEN(dev_priv) >= 11) in haswell_crtc_disable()
6547 return INTEL_GEN(dev_priv) < 4 && in intel_crtc_supports_double_wide()
6607 if (INTEL_GEN(dev_priv) < 4) { in intel_crtc_compute_config()
6660 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && in intel_crtc_compute_config()
6817 if (INTEL_GEN(dev_priv) >= 5) { in intel_cpu_transcoder_set_m_n()
6827 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { in intel_cpu_transcoder_set_m_n()
7211 if (INTEL_GEN(dev_priv) >= 4) in i9xx_compute_dpll()
7225 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_compute_dpll()
7298 if (INTEL_GEN(dev_priv) > 3) in intel_set_pipe_timings()
7457 if (INTEL_GEN(dev_priv) < 4 || in i9xx_set_pipeconf()
7668 if (INTEL_GEN(dev_priv) <= 3 && in i9xx_get_pfit_config()
7677 if (INTEL_GEN(dev_priv) < 4) { in i9xx_get_pfit_config()
7748 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_get_initial_plane_config()
7762 } else if (INTEL_GEN(dev_priv) >= 4) { in i9xx_get_initial_plane_config()
7868 if (INTEL_GEN(dev_priv) < 4) in i9xx_get_pipe_config()
7876 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_get_pipe_config()
8436 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { in haswell_set_pipemisc()
8667 if (INTEL_GEN(dev_priv) >= 5) { in intel_cpu_transcoder_get_m_n()
8679 if (m2_n2 && INTEL_GEN(dev_priv) < 8 && in intel_cpu_transcoder_get_m_n()
8780 if (INTEL_GEN(dev_priv) >= 11) in skylake_get_initial_plane_config()
8785 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { in skylake_get_initial_plane_config()
9476 if (INTEL_GEN(dev_priv) < 9 && in haswell_get_ddi_port_state()
9526 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { in haswell_get_pipe_config()
9530 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) { in haswell_get_pipe_config()
9546 if (INTEL_GEN(dev_priv) >= 9) in haswell_get_pipe_config()
9820 if (INTEL_GEN(dev_priv) <= 10) { in i9xx_cursor_ctl()
9827 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in i9xx_cursor_ctl()
10029 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_cursor_get_hw_state()
10529 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
10578 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
10585 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()
10592 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_plane_atomic_calc_changes()
10709 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) in intel_crtc_atomic_check()
10713 if (INTEL_GEN(dev_priv) >= 9) { in intel_crtc_atomic_check()
10801 else if (INTEL_GEN(dev_priv) >= 5) in compute_baseline_pipe_bpp()
10943 if (INTEL_GEN(dev_priv) >= 9) in intel_dump_pipe_config()
10984 if (INTEL_GEN(dev_priv) >= 9) in intel_dump_pipe_config()
11473 if (INTEL_GEN(dev_priv) < 8) { in intel_pipe_config_compare()
11499 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || in intel_pipe_config_compare()
11526 if (INTEL_GEN(dev_priv) < 4) in intel_pipe_config_compare()
11582 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) in intel_pipe_config_compare()
11632 if (INTEL_GEN(dev_priv) < 9 || !new_state->active) in verify_wm_state()
11641 if (INTEL_GEN(dev_priv) >= 11) in verify_wm_state()
12463 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) in skl_update_crtcs()
12518 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) in skl_update_crtcs()
12640 if (INTEL_GEN(dev_priv) >= 9) in intel_atomic_commit_tail()
12835 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { in intel_atomic_commit()
12942 if (INTEL_GEN(to_i915(crtc->dev)) < 6) in add_rps_boost_after_vblank()
13173 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) in skl_max_scale()
13206 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_primary_plane()
13228 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_primary_plane()
13242 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in intel_check_primary_plane()
13277 else if (INTEL_GEN(dev_priv) >= 9) in intel_begin_crtc_commit()
13607 else if (INTEL_GEN(dev_priv) >= 4) in i9xx_plane_has_fbc()
13628 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) && in skl_plane_has_planar()
13634 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) { in skl_plane_has_planar()
13674 if (INTEL_GEN(dev_priv) >= 9) { in intel_primary_plane_create()
13683 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) in intel_primary_plane_create()
13690 if (INTEL_GEN(dev_priv) >= 9) in intel_primary_plane_create()
13706 if (INTEL_GEN(dev_priv) >= 9) { in intel_primary_plane_create()
13728 } else if (INTEL_GEN(dev_priv) >= 4) { in intel_primary_plane_create()
13750 if (INTEL_GEN(dev_priv) >= 9) in intel_primary_plane_create()
13757 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_primary_plane_create()
13775 if (INTEL_GEN(dev_priv) >= 10) { in intel_primary_plane_create()
13780 } else if (INTEL_GEN(dev_priv) >= 9) { in intel_primary_plane_create()
13788 } else if (INTEL_GEN(dev_priv) >= 4) { in intel_primary_plane_create()
13795 if (INTEL_GEN(dev_priv) >= 4) in intel_primary_plane_create()
13800 if (INTEL_GEN(dev_priv) >= 9) in intel_primary_plane_create()
13877 if (INTEL_GEN(dev_priv) >= 4) in intel_cursor_plane_create()
13883 if (INTEL_GEN(dev_priv) >= 9) in intel_cursor_plane_create()
13981 if (INTEL_GEN(dev_priv) < 9) { in intel_crtc_init()
14070 if (INTEL_GEN(dev_priv) >= 9) in intel_crt_present()
14377 u32 gen = INTEL_GEN(dev_priv); in intel_fb_pitch_limit()
14458 if (INTEL_GEN(dev_priv) < 9) { in intel_framebuffer_init()
14476 if (INTEL_GEN(dev_priv) < 4 && in intel_framebuffer_init()
14510 if (INTEL_GEN(dev_priv) > 3) { in intel_framebuffer_init()
14518 INTEL_GEN(dev_priv) < 9) { in intel_framebuffer_init()
14527 if (INTEL_GEN(dev_priv) < 4) { in intel_framebuffer_init()
14544 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_framebuffer_init()
14551 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) || in intel_framebuffer_init()
14699 if (INTEL_GEN(dev_priv) >= 9 || in intel_mode_valid()
14705 } else if (INTEL_GEN(dev_priv) >= 3) { in intel_mode_valid()
14752 if (INTEL_GEN(dev_priv) >= 9) { in intel_init_display_hooks()
14831 if (INTEL_GEN(dev_priv) >= 9) in intel_init_display_hooks()
15384 if (INTEL_GEN(dev_priv) >= 4) in intel_sanitize_plane_mapping()
15838 } else if (INTEL_GEN(dev_priv) >= 9) { in intel_modeset_setup_hw_state()
15990 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_modeset_vga_set_state()
16096 if (INTEL_GEN(dev_priv) <= 3) { in intel_display_capture_error_state()
16100 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) in intel_display_capture_error_state()
16102 if (INTEL_GEN(dev_priv) >= 4) { in intel_display_capture_error_state()
16167 if (INTEL_GEN(dev_priv) <= 3) { in intel_display_print_error_state()
16171 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) in intel_display_print_error_state()
16173 if (INTEL_GEN(dev_priv) >= 4) { in intel_display_print_error_state()