2575 	if (INTEL_GEN(dev_priv) >= 8)  in ilk_display_fifo_size()
2577 	else if (INTEL_GEN(dev_priv) >= 7)  in ilk_display_fifo_size()
2587 	if (INTEL_GEN(dev_priv) >= 8)  in ilk_plane_wm_reg_max()
2590 	else if (INTEL_GEN(dev_priv) >= 7)  in ilk_plane_wm_reg_max()
2604 	if (INTEL_GEN(dev_priv) >= 7)  in ilk_cursor_wm_reg_max()
2612 	if (INTEL_GEN(dev_priv) >= 8)  in ilk_fbc_wm_reg_max()
2641 		if (INTEL_GEN(dev_priv) <= 6)  in ilk_plane_wm_max()
2802 	if (INTEL_GEN(dev_priv) >= 9) {  in intel_read_wm_latency()
2887 	} else if (INTEL_GEN(dev_priv) >= 6) {  in intel_read_wm_latency()
2894 	} else if (INTEL_GEN(dev_priv) >= 5) {  in intel_read_wm_latency()
2925 	if (INTEL_GEN(dev_priv) >= 9)  in ilk_wm_max_level()
2929 	else if (INTEL_GEN(dev_priv) >= 6)  in ilk_wm_max_level()
2954 		if (INTEL_GEN(dev_priv) >= 9)  in intel_print_wm_latency()
3090 	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)  in ilk_compute_pipe_wm()
3235 	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&  in ilk_wm_merge()
3240 	merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;  in ilk_wm_merge()
3330 		if (INTEL_GEN(dev_priv) >= 8)  in ilk_compute_wm_results()
3341 		if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {  in ilk_compute_wm_results()
3546 	if (INTEL_GEN(dev_priv) >= 7) {  in ilk_write_wm_values()
3578 	if (INTEL_GEN(dev_priv) < 11)  in intel_enabled_dbuf_slices_num()
3786 	if (INTEL_GEN(dev_priv) < 11)  in intel_get_ddb_size()
3872 	if (INTEL_GEN(dev_priv) >= 11)  in skl_ddb_entry_init_from_hw()
4088 	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)  in skl_check_pipe_max_pixel_rate()
4413 	if (INTEL_GEN(dev_priv) >= 10)  in skl_wm_method1()
4530 	if (INTEL_GEN(dev_priv) >= 11 &&  in skl_compute_plane_wm_params()
4565 		if (INTEL_GEN(dev_priv) >= 10)  in skl_compute_plane_wm_params()
4673 	if (INTEL_GEN(dev_priv) >= 11) {  in skl_compute_plane_wm()
4830 	if (INTEL_GEN(dev_priv) <= 9)  in skl_compute_transition_wm()
4838 	if (INTEL_GEN(dev_priv) >= 10)  in skl_compute_transition_wm()
4980 	if (INTEL_GEN(dev_priv) >= 11)  in skl_write_plane_wm()
5422 	if (INTEL_GEN(dev_priv) >= 7 &&  in ilk_program_watermarks()
6025 	if (INTEL_GEN(dev_priv) >= 7) {  in ilk_wm_get_hw_state()
6254 	if (INTEL_GEN(dev_priv) >= 9) {  in intel_rps_limits()
6389 	if (INTEL_GEN(i915) < 6)  in intel_rps_mark_interactive()
6432 		if (INTEL_GEN(dev_priv) >= 9)  in gen6_set_rps()
6783 	    IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {  in gen6_init_rps_frequencies()
6796 	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {  in gen6_init_rps_frequencies()
6863 	if (INTEL_GEN(dev_priv) >= 10) {  in gen9_enable_rc6()
7134 	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {  in gen6_update_ring_freq()
7149 		if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {  in gen6_update_ring_freq()
7155 		} else if (INTEL_GEN(dev_priv) >= 8) {  in gen6_update_ring_freq()
8172 	else if (INTEL_GEN(dev_priv) >= 6)  in intel_init_gt_powersave()
8227 	if (INTEL_GEN(dev_priv) < 6)  in intel_suspend_gt_powersave()
8239 	if (INTEL_GEN(dev_priv) >= 11)  in intel_sanitize_gt_powersave()
8264 	if (INTEL_GEN(dev_priv) >= 9)  in intel_disable_rc6()
8270 	else if (INTEL_GEN(dev_priv) >= 6)  in intel_disable_rc6()
8283 	if (INTEL_GEN(dev_priv) >= 9)  in intel_disable_rps()
8289 	else if (INTEL_GEN(dev_priv) >= 6)  in intel_disable_rps()
8332 	else if (INTEL_GEN(dev_priv) >= 9)  in intel_enable_rc6()
8336 	else if (INTEL_GEN(dev_priv) >= 6)  in intel_enable_rc6()
8355 	} else if (INTEL_GEN(dev_priv) >= 9) {  in intel_enable_rps()
8359 	} else if (INTEL_GEN(dev_priv) >= 6) {  in intel_enable_rps()
9289 	if (INTEL_GEN(dev_priv) >= 9) {  in intel_init_pm()
9435 	if (INTEL_GEN(dev_priv) > 6)  in sandybridge_pcode_read()
9483 	if (INTEL_GEN(dev_priv) > 6)  in sandybridge_pcode_write_timeout()
9612 	if (INTEL_GEN(dev_priv) >= 9)  in intel_gpu_freq()
9625 	if (INTEL_GEN(dev_priv) >= 9)  in intel_freq_opcode()
9771 	if (INTEL_GEN(dev_priv) >= 9)  in intel_get_cagf()