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Searched refs:HIWORD_UPDATE (Results 1 – 24 of 24) sorted by relevance

/Linux-v4.19/drivers/soc/rockchip/
Dgrf.c17 #define HIWORD_UPDATE(val, mask, shift) \ macro
38 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
49 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
60 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
71 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
82 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
93 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
104 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
/Linux-v4.19/drivers/phy/rockchip/
Dphy-rockchip-emmc.c31 #define HIWORD_UPDATE(val, mask, shift) \ macro
107 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
112 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
165 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
188 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
194 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
287 HIWORD_UPDATE(PHYCTRL_DR_50OHM, in rockchip_emmc_phy_power_on()
294 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
301 HIWORD_UPDATE(4, in rockchip_emmc_phy_power_on()
Dphy-rockchip-pcie.c34 #define HIWORD_UPDATE(val, mask, shift) \ macro
112 HIWORD_UPDATE(data, in phy_wr_cfg()
115 HIWORD_UPDATE(addr, in phy_wr_cfg()
120 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
125 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
136 HIWORD_UPDATE(addr, in phy_rd_cfg()
155 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
176 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
203 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
209 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_on()
[all …]
Dphy-rockchip-usb.c36 #define HIWORD_UPDATE(val, mask) \ macro
75 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
366 val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N in rk3288_init_usb_uart()
376 val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL, in rk3288_init_usb_uart()
382 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING in rk3288_init_usb_uart()
393 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL in rk3288_init_usb_uart()
/Linux-v4.19/drivers/clk/rockchip/
Dclk-pll.c212 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
214 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
218 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
220 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
270 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
281 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
443 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
447 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
449 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
[all …]
Dclk-cpu.c168 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
170 HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
176 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
212 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, in rockchip_cpuclk_post_rate_change()
214 HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
Dclk-rk3188.c120 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
126 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
128 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
130 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
132 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
171 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
Dclk-inverter.c58 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
Dclk-rk3288.c121 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
123 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
129 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
131 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
133 HIWORD_UPDATE(_pclk_dbg_pre, \
Dclk-mmc-phase.c149 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
Dclk-rk3036.c94 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
458 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), in rk3036_clk_init()
Dclk-rk3368.c194 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
200 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
202 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
Dclk-rk3128.c91 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
93 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
Dclk-rk3228.c92 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
94 HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
Dclk-rk3328.c104 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
106 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
Dclk-rk3399.c329 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
335 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
337 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
Dclk-px30.c89 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
91 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
Dclk.h34 #define HIWORD_UPDATE(val, mask, shift) \ macro
Dclk-rv1108.c83 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
/Linux-v4.19/drivers/pci/controller/
Dpcie-rockchip.h21 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
22 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
35 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
38 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
/Linux-v4.19/drivers/gpu/drm/rockchip/
Ddw_hdmi-rockchip.c30 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
292 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
293 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
306 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
307 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
Danalogix_dp-rockchip.c43 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
446 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
447 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
453 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
454 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/Linux-v4.19/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-rk.c77 #define HIWORD_UPDATE(val, mask, shift) \ macro
153 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
154 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
262 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
263 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
408 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
409 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
500 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
501 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
652 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
[all …]
/Linux-v4.19/drivers/mmc/host/
Dsdhci-of-arasan.c45 #define HIWORD_UPDATE(val, mask, shift) \ macro
151 HIWORD_UPDATE(val, GENMASK(width, 0), in sdhci_arasan_syscon_write()