1 /*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #include <drm/drm_of.h>
17 #include <drm/drmP.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/bridge/dw_hdmi.h>
21
22 #include "rockchip_drm_drv.h"
23 #include "rockchip_drm_vop.h"
24
25 #define RK3288_GRF_SOC_CON6 0x025C
26 #define RK3288_HDMI_LCDC_SEL BIT(4)
27 #define RK3399_GRF_SOC_CON20 0x6250
28 #define RK3399_HDMI_LCDC_SEL BIT(6)
29
30 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
31
32 /**
33 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
34 * @lcdsel_grf_reg: grf register offset of lcdc select
35 * @lcdsel_big: reg value of selecting vop big for HDMI
36 * @lcdsel_lit: reg value of selecting vop little for HDMI
37 */
38 struct rockchip_hdmi_chip_data {
39 u32 lcdsel_grf_reg;
40 u32 lcdsel_big;
41 u32 lcdsel_lit;
42 };
43
44 struct rockchip_hdmi {
45 struct device *dev;
46 struct regmap *regmap;
47 struct drm_encoder encoder;
48 const struct rockchip_hdmi_chip_data *chip_data;
49 struct clk *vpll_clk;
50 struct clk *grf_clk;
51 struct dw_hdmi *hdmi;
52 };
53
54 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
55
56 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
57 {
58 27000000, {
59 { 0x00b3, 0x0000},
60 { 0x2153, 0x0000},
61 { 0x40f3, 0x0000}
62 },
63 }, {
64 36000000, {
65 { 0x00b3, 0x0000},
66 { 0x2153, 0x0000},
67 { 0x40f3, 0x0000}
68 },
69 }, {
70 40000000, {
71 { 0x00b3, 0x0000},
72 { 0x2153, 0x0000},
73 { 0x40f3, 0x0000}
74 },
75 }, {
76 54000000, {
77 { 0x0072, 0x0001},
78 { 0x2142, 0x0001},
79 { 0x40a2, 0x0001},
80 },
81 }, {
82 65000000, {
83 { 0x0072, 0x0001},
84 { 0x2142, 0x0001},
85 { 0x40a2, 0x0001},
86 },
87 }, {
88 66000000, {
89 { 0x013e, 0x0003},
90 { 0x217e, 0x0002},
91 { 0x4061, 0x0002}
92 },
93 }, {
94 74250000, {
95 { 0x0072, 0x0001},
96 { 0x2145, 0x0002},
97 { 0x4061, 0x0002}
98 },
99 }, {
100 83500000, {
101 { 0x0072, 0x0001},
102 },
103 }, {
104 108000000, {
105 { 0x0051, 0x0002},
106 { 0x2145, 0x0002},
107 { 0x4061, 0x0002}
108 },
109 }, {
110 106500000, {
111 { 0x0051, 0x0002},
112 { 0x2145, 0x0002},
113 { 0x4061, 0x0002}
114 },
115 }, {
116 146250000, {
117 { 0x0051, 0x0002},
118 { 0x2145, 0x0002},
119 { 0x4061, 0x0002}
120 },
121 }, {
122 148500000, {
123 { 0x0051, 0x0003},
124 { 0x214c, 0x0003},
125 { 0x4064, 0x0003}
126 },
127 }, {
128 ~0UL, {
129 { 0x00a0, 0x000a },
130 { 0x2001, 0x000f },
131 { 0x4002, 0x000f },
132 },
133 }
134 };
135
136 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
137 /* pixelclk bpp8 bpp10 bpp12 */
138 {
139 40000000, { 0x0018, 0x0018, 0x0018 },
140 }, {
141 65000000, { 0x0028, 0x0028, 0x0028 },
142 }, {
143 66000000, { 0x0038, 0x0038, 0x0038 },
144 }, {
145 74250000, { 0x0028, 0x0038, 0x0038 },
146 }, {
147 83500000, { 0x0028, 0x0038, 0x0038 },
148 }, {
149 146250000, { 0x0038, 0x0038, 0x0038 },
150 }, {
151 148500000, { 0x0000, 0x0038, 0x0038 },
152 }, {
153 ~0UL, { 0x0000, 0x0000, 0x0000},
154 }
155 };
156
157 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
158 /*pixelclk symbol term vlev*/
159 { 74250000, 0x8009, 0x0004, 0x0272},
160 { 148500000, 0x802b, 0x0004, 0x028d},
161 { 297000000, 0x8039, 0x0005, 0x028d},
162 { ~0UL, 0x0000, 0x0000, 0x0000}
163 };
164
rockchip_hdmi_parse_dt(struct rockchip_hdmi * hdmi)165 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
166 {
167 struct device_node *np = hdmi->dev->of_node;
168
169 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
170 if (IS_ERR(hdmi->regmap)) {
171 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
172 return PTR_ERR(hdmi->regmap);
173 }
174
175 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
176 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
177 hdmi->vpll_clk = NULL;
178 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
179 return -EPROBE_DEFER;
180 } else if (IS_ERR(hdmi->vpll_clk)) {
181 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
182 return PTR_ERR(hdmi->vpll_clk);
183 }
184
185 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
186 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
187 hdmi->grf_clk = NULL;
188 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
189 return -EPROBE_DEFER;
190 } else if (IS_ERR(hdmi->grf_clk)) {
191 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
192 return PTR_ERR(hdmi->grf_clk);
193 }
194
195 return 0;
196 }
197
198 static enum drm_mode_status
dw_hdmi_rockchip_mode_valid(struct drm_connector * connector,const struct drm_display_mode * mode)199 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
200 const struct drm_display_mode *mode)
201 {
202 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
203 int pclk = mode->clock * 1000;
204 bool valid = false;
205 int i;
206
207 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
208 if (pclk == mpll_cfg[i].mpixelclock) {
209 valid = true;
210 break;
211 }
212 }
213
214 return (valid) ? MODE_OK : MODE_BAD;
215 }
216
217 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
218 .destroy = drm_encoder_cleanup,
219 };
220
dw_hdmi_rockchip_encoder_disable(struct drm_encoder * encoder)221 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
222 {
223 }
224
225 static bool
dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)226 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
227 const struct drm_display_mode *mode,
228 struct drm_display_mode *adj_mode)
229 {
230 return true;
231 }
232
dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)233 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
234 struct drm_display_mode *mode,
235 struct drm_display_mode *adj_mode)
236 {
237 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
238
239 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
240 }
241
dw_hdmi_rockchip_encoder_enable(struct drm_encoder * encoder)242 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
243 {
244 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
245 u32 val;
246 int ret;
247
248 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
249 if (ret)
250 val = hdmi->chip_data->lcdsel_lit;
251 else
252 val = hdmi->chip_data->lcdsel_big;
253
254 ret = clk_prepare_enable(hdmi->grf_clk);
255 if (ret < 0) {
256 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
257 return;
258 }
259
260 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
261 if (ret != 0)
262 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
263
264 clk_disable_unprepare(hdmi->grf_clk);
265 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
266 ret ? "LIT" : "BIG");
267 }
268
269 static int
dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)270 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
271 struct drm_crtc_state *crtc_state,
272 struct drm_connector_state *conn_state)
273 {
274 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
275
276 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
277 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
278
279 return 0;
280 }
281
282 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
283 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
284 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
285 .enable = dw_hdmi_rockchip_encoder_enable,
286 .disable = dw_hdmi_rockchip_encoder_disable,
287 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
288 };
289
290 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
291 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
292 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
293 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
294 };
295
296 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
297 .mode_valid = dw_hdmi_rockchip_mode_valid,
298 .mpll_cfg = rockchip_mpll_cfg,
299 .cur_ctr = rockchip_cur_ctr,
300 .phy_config = rockchip_phy_config,
301 .phy_data = &rk3288_chip_data,
302 };
303
304 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
305 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
306 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
307 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
308 };
309
310 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
311 .mode_valid = dw_hdmi_rockchip_mode_valid,
312 .mpll_cfg = rockchip_mpll_cfg,
313 .cur_ctr = rockchip_cur_ctr,
314 .phy_config = rockchip_phy_config,
315 .phy_data = &rk3399_chip_data,
316 };
317
318 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
319 { .compatible = "rockchip,rk3288-dw-hdmi",
320 .data = &rk3288_hdmi_drv_data
321 },
322 { .compatible = "rockchip,rk3399-dw-hdmi",
323 .data = &rk3399_hdmi_drv_data
324 },
325 {},
326 };
327 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
328
dw_hdmi_rockchip_bind(struct device * dev,struct device * master,void * data)329 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
330 void *data)
331 {
332 struct platform_device *pdev = to_platform_device(dev);
333 const struct dw_hdmi_plat_data *plat_data;
334 const struct of_device_id *match;
335 struct drm_device *drm = data;
336 struct drm_encoder *encoder;
337 struct rockchip_hdmi *hdmi;
338 int ret;
339
340 if (!pdev->dev.of_node)
341 return -ENODEV;
342
343 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
344 if (!hdmi)
345 return -ENOMEM;
346
347 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
348 plat_data = match->data;
349 hdmi->dev = &pdev->dev;
350 hdmi->chip_data = plat_data->phy_data;
351 encoder = &hdmi->encoder;
352
353 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
354 /*
355 * If we failed to find the CRTC(s) which this encoder is
356 * supposed to be connected to, it's because the CRTC has
357 * not been registered yet. Defer probing, and hope that
358 * the required CRTC is added later.
359 */
360 if (encoder->possible_crtcs == 0)
361 return -EPROBE_DEFER;
362
363 ret = rockchip_hdmi_parse_dt(hdmi);
364 if (ret) {
365 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
366 return ret;
367 }
368
369 ret = clk_prepare_enable(hdmi->vpll_clk);
370 if (ret) {
371 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
372 ret);
373 return ret;
374 }
375
376 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
377 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
378 DRM_MODE_ENCODER_TMDS, NULL);
379
380 platform_set_drvdata(pdev, hdmi);
381
382 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
383
384 /*
385 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
386 * which would have called the encoder cleanup. Do it manually.
387 */
388 if (IS_ERR(hdmi->hdmi)) {
389 ret = PTR_ERR(hdmi->hdmi);
390 drm_encoder_cleanup(encoder);
391 clk_disable_unprepare(hdmi->vpll_clk);
392 }
393
394 return ret;
395 }
396
dw_hdmi_rockchip_unbind(struct device * dev,struct device * master,void * data)397 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
398 void *data)
399 {
400 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
401
402 dw_hdmi_unbind(hdmi->hdmi);
403 clk_disable_unprepare(hdmi->vpll_clk);
404 }
405
406 static const struct component_ops dw_hdmi_rockchip_ops = {
407 .bind = dw_hdmi_rockchip_bind,
408 .unbind = dw_hdmi_rockchip_unbind,
409 };
410
dw_hdmi_rockchip_probe(struct platform_device * pdev)411 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
412 {
413 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
414 }
415
dw_hdmi_rockchip_remove(struct platform_device * pdev)416 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
417 {
418 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
419
420 return 0;
421 }
422
423 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
424 .probe = dw_hdmi_rockchip_probe,
425 .remove = dw_hdmi_rockchip_remove,
426 .driver = {
427 .name = "dwhdmi-rockchip",
428 .of_match_table = dw_hdmi_rockchip_dt_ids,
429 },
430 };
431
