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Searched refs:GENMASK (Results 1 – 25 of 691) sorted by relevance

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/Linux-v4.19/drivers/net/ethernet/mscc/
Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
[all …]
Docelot_hsio.h16 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
17 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
18 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
19 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
20 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
21 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
22 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
23 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
24 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
29 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
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Docelot_qsys.h19 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
20 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
21 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
24 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
25 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
26 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
38 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
39 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
40 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
41 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
[all …]
Docelot_sys.h17 #define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5))
18 #define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5)
19 #define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5)
20 #define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3))
21 #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
22 #define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3)
23 #define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1))
24 #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
25 #define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1)
33 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
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Docelot_dev.h19 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
20 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
35 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
36 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
37 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
38 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
39 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
40 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
41 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
42 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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Docelot_qs.h24 #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
25 #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
26 #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
34 #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5))
35 #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5)
36 #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5)
37 #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2))
38 #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)
39 #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2)
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0))
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Docelot_dev_gmii.h17 #define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
34 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
35 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
36 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
37 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
38 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
39 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
40 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
41 #define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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Docelot_rew.h13 #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16))
14 #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16)
15 #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16)
17 #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12))
18 #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12)
19 #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
20 #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0))
21 #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0)
25 #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7))
26 #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7)
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/Linux-v4.19/drivers/infiniband/hw/hns/
Dhns_roce_hw_v2.h256 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
267 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
270 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
273 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
276 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
279 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
282 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
285 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
288 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
291 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
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/Linux-v4.19/drivers/media/platform/ti-vpe/
Dcal_regs.h94 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
95 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
96 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
97 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
98 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
99 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
103 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
104 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
105 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
106 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
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/Linux-v4.19/drivers/mtd/nand/raw/
Ddenali.h31 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
34 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
37 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
40 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
62 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
74 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
75 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
79 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
80 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
83 #define RE_2_WE__VALUE GENMASK(5, 0)
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/Linux-v4.19/drivers/net/wireless/mediatek/mt76/
Dmt76x2_regs.h30 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
31 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
33 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
34 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
60 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
61 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
62 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
71 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
74 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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Ddma.h21 #define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0)
24 #define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16)
28 #define MT_TXD_INFO_LEN GENMASK(15, 0)
35 #define MT_TXD_INFO_QSEL GENMASK(26, 25)
36 #define MT_TXD_INFO_DPORT GENMASK(29, 27)
37 #define MT_TXD_INFO_TYPE GENMASK(31, 30)
39 #define MT_RX_FCE_INFO_LEN GENMASK(13, 0)
41 #define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)
42 #define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)
44 #define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)
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/Linux-v4.19/drivers/net/wireless/mediatek/mt7601u/
Dregs.h30 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
31 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
33 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
34 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
60 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
61 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
62 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
71 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
74 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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Dmac.h73 #define MT_RXINFO_PN_LEN GENMASK(21, 19)
80 #define MT_RXWI_CTL_WCID GENMASK(7, 0)
81 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
82 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
83 #define MT_RXWI_CTL_UDF GENMASK(15, 13)
84 #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16)
85 #define MT_RXWI_CTL_TID GENMASK(31, 28)
87 #define MT_RXWI_FRAG GENMASK(3, 0)
88 #define MT_RXWI_SN GENMASK(15, 4)
90 #define MT_RXWI_RATE_MCS GENMASK(6, 0)
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/Linux-v4.19/drivers/net/wireless/mediatek/mt76/mt76x0/
Dregs.h31 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
32 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
33 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
34 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
35 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
66 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
67 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
68 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
77 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
80 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
[all …]
Dmac.h54 #define MT_RXINFO_PN_LEN GENMASK(21, 19)
61 #define MT_RXWI_CTL_WCID GENMASK(7, 0)
62 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
63 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
64 #define MT_RXWI_CTL_UDF GENMASK(15, 13)
65 #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16)
66 #define MT_RXWI_CTL_TID GENMASK(31, 28)
68 #define MT_RXWI_FRAG GENMASK(3, 0)
69 #define MT_RXWI_SN GENMASK(15, 4)
71 #define MT_RXWI_RATE_INDEX GENMASK(5, 0)
[all …]
/Linux-v4.19/include/linux/mfd/syscon/
Datmel-mc.h25 #define AT91_MC_ABTSZ GENMASK(9, 8)
29 #define AT91_MC_ABTTYP GENMASK(11, 10)
39 #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
51 #define AT91_MC_SMC_NWS GENMASK(6, 0)
54 #define AT91_MC_SMC_TDF GENMASK(11, 8)
58 #define AT91_MC_SMC_DBW GENMASK(14, 13)
62 #define AT91_MC_SMC_ACSS GENMASK(17, 16)
65 #define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
67 #define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
73 #define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
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/Linux-v4.19/arch/mips/include/asm/
Dmips-cm.h137 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
138 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
139 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
144 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
152 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
156 #define CM_GCR_REV_MAJOR GENMASK(15, 8)
157 #define CM_GCR_REV_MINOR GENMASK(7, 0)
178 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
180 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
187 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
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/Linux-v4.19/drivers/net/ethernet/stmicro/stmmac/
Ddwxgmac2.h18 #define XGMAC_CONFIG_SS_MASK GENMASK(30, 29)
22 #define XGMAC_CONFIG_SARC GENMASK(22, 20)
29 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
47 #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
51 #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
61 #define XGMAC_PT GENMASK(31, 16)
84 #define XGMAC_HWFEAT_TXFIFOSIZE GENMASK(10, 6)
85 #define XGMAC_HWFEAT_RXFIFOSIZE GENMASK(4, 0)
87 #define XGMAC_HWFEAT_PPSOUTNUM GENMASK(26, 24)
88 #define XGMAC_HWFEAT_TXCHCNT GENMASK(21, 18)
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Ddwmac4.h48 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
50 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
52 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
54 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
56 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
71 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
79 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
83 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
142 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
149 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
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Ddwmac4_descs.h22 #define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)
23 #define TDES2_VLAN_TAG_MASK GENMASK(15, 14)
24 #define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)
30 #define TDES3_PACKET_SIZE_MASK GENMASK(14, 0)
31 #define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
33 #define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
36 #define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
37 #define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
38 #define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
45 #define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4)
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/Linux-v4.19/include/linux/mfd/
Dtps68470.h57 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)
58 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
60 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
61 #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)
62 #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)
63 #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)
64 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)
65 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)
67 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
68 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
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/Linux-v4.19/include/linux/amba/
Dpl080.h73 #define PL080_LLI_ADDR_MASK GENMASK(31, 2)
78 #define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
87 #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
89 #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
91 #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
93 #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
95 #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
96 #define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
119 #define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
121 #define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
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/Linux-v4.19/sound/soc/uniphier/
Daio-reg.h32 #define A2APLLCTR0_APLLXPOW_MASK GENMASK(3, 0)
40 #define A2EXMCLKSEL0_EXMCLK_MASK GENMASK(2, 0)
46 #define A2AIOINPUTSEL_RXSEL_PCMI1_MASK GENMASK(2, 0)
48 #define A2AIOINPUTSEL_RXSEL_PCMI2_MASK GENMASK(6, 4)
50 #define A2AIOINPUTSEL_RXSEL_PCMI3_MASK GENMASK(10, 8)
52 #define A2AIOINPUTSEL_RXSEL_IECI1_MASK GENMASK(14, 12)
67 #define IPORTMXCTR1_LRSEL_MASK GENMASK(11, 10)
76 #define IPORTMXCTR1_CHSEL_MASK GENMASK(6, 4)
83 #define IPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)
98 #define IPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)
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