Lines Matching refs:GENMASK
30 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
31 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
33 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
34 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
60 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
61 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
62 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
71 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
74 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
79 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
80 #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
89 #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)
97 #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
112 #define MT_INT_TX_DONE_ALL GENMASK(13, 4)
131 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
134 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
143 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
147 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
151 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
157 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
169 #define MT_US_CYC_CNT GENMASK(7, 0)
199 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
217 #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
218 #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
219 #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
240 #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
244 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
245 #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
246 #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
250 #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
269 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
273 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
274 #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
275 #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
276 #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
280 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
281 #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
290 #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)
291 #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)
296 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
298 #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
301 #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
307 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
308 #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
338 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
339 #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
340 #define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
341 #define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
349 #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
370 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
371 #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
375 #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)
381 #define MT_PROT_CFG_RATE GENMASK(15, 0)
382 #define MT_PROT_CFG_CTRL GENMASK(17, 16)
383 #define MT_PROT_CFG_NAV GENMASK(19, 18)
384 #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)
400 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
401 #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
410 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
411 #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
412 #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
413 #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
416 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
419 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
460 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
461 #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
462 #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
463 #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
464 #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
465 #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
474 #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)
475 #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)
478 #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
479 #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)
482 #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
483 #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)
486 #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
487 #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)
498 #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
499 #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
509 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
510 #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)
532 #define MT_BBP_CORE_R1_BW GENMASK(4, 3)
534 #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
535 #define MT_BBP_AGC_R0_BW GENMASK(14, 12)
538 #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)
539 #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)
540 #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)
543 #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)
546 #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)
547 #define MT_BBP_AGC_GAIN GENMASK(14, 8)
549 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
550 #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
552 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
569 #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
570 #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
571 #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
575 #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
588 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
594 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)