1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __MT76_MAC_H 16 #define __MT76_MAC_H 17 18 /* Note: values in original "RSSI" and "SNR" fields are not actually what they 19 * are called for MT76X0U, names used by this driver are educated guesses 20 * (see vendor mac/ral_omac.c). 21 */ 22 struct mt76x0_rxwi { 23 __le32 rxinfo; 24 25 __le32 ctl; 26 27 __le16 tid_sn; 28 __le16 rate; 29 30 s8 rssi[4]; 31 32 __le32 bbp_rxinfo[4]; 33 } __packed __aligned(4); 34 35 #define MT_RXINFO_BA BIT(0) 36 #define MT_RXINFO_DATA BIT(1) 37 #define MT_RXINFO_NULL BIT(2) 38 #define MT_RXINFO_FRAG BIT(3) 39 #define MT_RXINFO_U2M BIT(4) 40 #define MT_RXINFO_MULTICAST BIT(5) 41 #define MT_RXINFO_BROADCAST BIT(6) 42 #define MT_RXINFO_MYBSS BIT(7) 43 #define MT_RXINFO_CRCERR BIT(8) 44 #define MT_RXINFO_ICVERR BIT(9) 45 #define MT_RXINFO_MICERR BIT(10) 46 #define MT_RXINFO_AMSDU BIT(11) 47 #define MT_RXINFO_HTC BIT(12) 48 #define MT_RXINFO_RSSI BIT(13) 49 #define MT_RXINFO_L2PAD BIT(14) 50 #define MT_RXINFO_AMPDU BIT(15) 51 #define MT_RXINFO_DECRYPT BIT(16) 52 #define MT_RXINFO_BSSIDX3 BIT(17) 53 #define MT_RXINFO_WAPI_KEY BIT(18) 54 #define MT_RXINFO_PN_LEN GENMASK(21, 19) 55 #define MT_RXINFO_SW_PKT_80211 BIT(22) 56 #define MT_RXINFO_TCP_SUM_BYPASS BIT(28) 57 #define MT_RXINFO_IP_SUM_BYPASS BIT(29) 58 #define MT_RXINFO_TCP_SUM_ERR BIT(30) 59 #define MT_RXINFO_IP_SUM_ERR BIT(31) 60 61 #define MT_RXWI_CTL_WCID GENMASK(7, 0) 62 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) 63 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) 64 #define MT_RXWI_CTL_UDF GENMASK(15, 13) 65 #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16) 66 #define MT_RXWI_CTL_TID GENMASK(31, 28) 67 68 #define MT_RXWI_FRAG GENMASK(3, 0) 69 #define MT_RXWI_SN GENMASK(15, 4) 70 71 #define MT_RXWI_RATE_INDEX GENMASK(5, 0) 72 #define MT_RXWI_RATE_LDPC BIT(6) 73 #define MT_RXWI_RATE_BW GENMASK(8, 7) 74 #define MT_RXWI_RATE_SGI BIT(9) 75 #define MT_RXWI_RATE_STBC BIT(10) 76 #define MT_RXWI_RATE_LDPC_ETXBF BIT(11) 77 #define MT_RXWI_RATE_SND BIT(12) 78 #define MT_RXWI_RATE_PHY GENMASK(15, 13) 79 80 #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0) 81 #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4) 82 83 #define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0) 84 #define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6) 85 #define MT_RXWI_ANT_AUX_LNA BIT(7) 86 87 #define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0) 88 89 enum mt76_phy_bandwidth { 90 MT_PHY_BW_20, 91 MT_PHY_BW_40, 92 MT_PHY_BW_80, 93 }; 94 95 struct mt76_txwi { 96 __le16 flags; 97 __le16 rate_ctl; 98 u8 ack_ctl; 99 u8 wcid; 100 __le16 len_ctl; 101 __le32 iv; 102 __le32 eiv; 103 u8 aid; 104 u8 txstream; 105 u8 ctl2; 106 u8 pktid; 107 } __packed __aligned(4); 108 109 #define MT_TXWI_FLAGS_FRAG BIT(0) 110 #define MT_TXWI_FLAGS_MMPS BIT(1) 111 #define MT_TXWI_FLAGS_CFACK BIT(2) 112 #define MT_TXWI_FLAGS_TS BIT(3) 113 #define MT_TXWI_FLAGS_AMPDU BIT(4) 114 #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) 115 #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) 116 #define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10) 117 #define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) 118 #define MT_TXWI_FLAGS_TX_RPT BIT(14) 119 #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) 120 121 #define MT_TXWI_RATE_MCS GENMASK(6, 0) 122 #define MT_TXWI_RATE_BW BIT(7) 123 #define MT_TXWI_RATE_SGI BIT(8) 124 #define MT_TXWI_RATE_STBC GENMASK(10, 9) 125 #define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14) 126 127 #define MT_TXWI_ACK_CTL_REQ BIT(0) 128 #define MT_TXWI_ACK_CTL_NSEQ BIT(1) 129 #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) 130 131 #define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0) 132 133 #define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0) 134 #define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) 135 #define MT_TXWI_CTL_PIFS_REV BIT(6) 136 137 #define MT_TXWI_PKTID_PROBE BIT(7) 138 139 u32 mt76x0_mac_process_rx(struct mt76x0_dev *dev, struct sk_buff *skb, 140 u8 *data, void *rxi); 141 int mt76x0_mac_wcid_set_key(struct mt76x0_dev *dev, u8 idx, 142 struct ieee80211_key_conf *key); 143 void mt76x0_mac_wcid_set_rate(struct mt76x0_dev *dev, struct mt76_wcid *wcid, 144 const struct ieee80211_tx_rate *rate); 145 146 int mt76x0_mac_shared_key_setup(struct mt76x0_dev *dev, u8 vif_idx, u8 key_idx, 147 struct ieee80211_key_conf *key); 148 u16 mt76x0_mac_tx_rate_val(struct mt76x0_dev *dev, 149 const struct ieee80211_tx_rate *rate, u8 *nss_val); 150 struct mt76_tx_status 151 mt76x0_mac_fetch_tx_status(struct mt76x0_dev *dev); 152 void mt76x0_send_tx_status(struct mt76x0_dev *dev, struct mt76_tx_status *stat, u8 *update); 153 154 #endif 155
