Searched refs:FPGA (Results 1 – 25 of 158) sorted by relevance
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| /Linux-v4.19/drivers/fpga/ |
| D | Kconfig | 2 # FPGA framework configuration
5 menuconfig FPGA config
6 tristate "FPGA Configuration Framework"
9 kernel. The FPGA framework adds a FPGA manager class and FPGA
12 if FPGA
15 tristate "Altera SOCFPGA FPGA Manager"
18 FPGA manager driver support for Altera SOCFPGA.
25 FPGA manager driver support for Altera Arria10 SoCFPGA.
40 tristate "Altera FPGA Passive Serial over SPI"
43 FPGA manager driver support for Altera Arria/Cyclone/Stratix
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| /Linux-v4.19/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.txt | 1 FPGA Region Device Tree Binding
9 - FPGA Region
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
23 attempts to include terminology used by both major FPGA manufacturers. This
24 document isn't a replacement for any manufacturers specifications for FPGA
32 * The entire FPGA is programmed.
35 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
37 * Not all FPGA's support PR.
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| D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
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| D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
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| D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
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| /Linux-v4.19/Documentation/driver-api/fpga/ |
| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
32 FPGA Bridge
35 FPGA Bridges prevent spurious signals from going out of an FPGA or a
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| D | fpga-region.rst | 1 FPGA Region
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
18 to program the FPGA and then DT to handle enumeration. The common region code
24 * which FPGA manager to use to do the programming
28 Additional info needed to program the FPGA image is passed in the struct
37 How to program an FPGA using a region
50 Point to your FPGA image, such as::
63 * lock the region's FPGA manager
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| D | fpga-mgr.rst | 1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
26 To add another FPGA manager, write a driver that implements a set of ops. The
52 mgr = fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
77 do the programming sequence for this particular FPGA. These ops return 0 for
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| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
25 API to control an FPGA bridge
28 You probably won't need these directly. FPGA regions should handle this.
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| /Linux-v4.19/drivers/staging/gs_fpgaboot/ |
| D | README | 2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
21 An FPGA (Field Programmable Gate Array) is a programmable hardware that is
24 This driver provides a way to download FPGA firmware.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
31 - FPGA prgram is done by gpio based bit-banging, as an example
42 a. As a FPGA development support tool,
43 During FPGA firmware development, you need to download a new FPGA
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| D | Kconfig | 2 # "xilinx FPGA firmware download, fpgaboot"
5 tristate "Xilinx FPGA firmware download module"
8 Xilinx FPGA firmware download module
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| /Linux-v4.19/Documentation/ABI/testing/ |
| D | sysfs-class-fpga-manager | 13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
26 * power up = FPGA reports power is up
27 * reset = FPGA held in reset state
30 * write init = preparing FPGA for programming
31 * write init error = Error while preparing FPGA for
33 * write = FPGA ready to receive image data
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| D | sysfs-platform-dfl-fme | 5 Description: Read-only. One DFL FPGA device may have more than 1
7 number of ports on the FPGA device when read it.
13 Description: Read-only. It returns Bitstream (static FPGA region)
15 and other information of this static FPGA region.
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
23 information of this static FPGA region.
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| D | sysfs-bus-mcb | 11 Description: The FPGA's revision number
17 Description: The FPGA's minor number
23 Description: The FPGA's model number
29 Description: The FPGA's name
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| D | sysfs-class-fpga-region | 5 Description: FPGA region id for compatibility check, e.g. compatibility
6 of the FPGA reconfiguration hardware and image. This value
8 FPGA region. This interface returns the compat_id value or
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| D | sysfs-platform-dfl-port | 5 Description: Read-only. It returns id of this port. One DFL FPGA device
7 distinguish different ports under same FPGA device.
13 Description: Read-only. User can program different PR bitstreams to FPGA
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| /Linux-v4.19/Documentation/fpga/ |
| D | dfl.txt | 2 FPGA Device Feature List (DFL) Framework Overview
8 The Device Feature List (DFL) FPGA framework (and drivers according to this
11 configure, enumerate, open and access FPGA accelerators on platforms which
13 enables system level management functions such as FPGA reconfiguration.
20 walk through these predefined data structures to enumerate FPGA features:
21 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
52 FPGA Interface Unit (FIU) represents a standalone functional unit for the
53 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
56 Accelerated Function Unit (AFU) represents a FPGA programmable region and
71 and can be implemented in register regions of any FPGA device.
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| /Linux-v4.19/Documentation/devicetree/bindings/bus/ |
| D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
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| /Linux-v4.19/Documentation/ |
| D | xillybus.txt | 2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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| /Linux-v4.19/Documentation/devicetree/bindings/board/ |
| D | fsl-board.txt | 20 * Freescale on-board FPGA
22 This is the memory-mapped registers for on board FPGA.
26 indicating the type of FPGA. Example:
29 - reg: should contain the address and the length of the FPGA register set.
80 * Freescale on-board FPGA connected on I2C bus
82 Some Freescale boards like BSC9132QDS have on board FPGA connected on
87 indicating the type of FPGA. Example:
89 - reg: Should contain the address of the FPGA
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| /Linux-v4.19/drivers/misc/altera-stapl/ |
| D | Kconfig | 1 comment "Altera FPGA firmware download module (requires I2C)"
5 tristate "Altera FPGA firmware download module"
9 An Altera FPGA module. Say Y when you want to support this tool.
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| /Linux-v4.19/Documentation/devicetree/bindings/gpio/ |
| D | gpio-ts4900.txt | 1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
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| /Linux-v4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
34 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
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| /Linux-v4.19/drivers/char/xillybus/ |
| D | Kconfig | 6 tristate "Xillybus generic FPGA interface"
11 programmable logic (FPGA). The driver probes the hardware for
23 with the FPGA.
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| /Linux-v4.19/Documentation/fmc/ |
| D | API.txt | 32 registered at the same time because if the FPGA is reprogrammed, all
34 first device will reprogram the FPGA, so other devices must know they
35 are already driven by a reprogrammed FPGA.
37 If a carrier hosts slots that are driven by different FPGA devices, it
39 FPGA, for the reason outlined above.
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