Lines Matching refs:FPGA
2 # FPGA framework configuration
5 menuconfig FPGA config
6 tristate "FPGA Configuration Framework"
9 kernel. The FPGA framework adds a FPGA manager class and FPGA
12 if FPGA
15 tristate "Altera SOCFPGA FPGA Manager"
18 FPGA manager driver support for Altera SOCFPGA.
25 FPGA manager driver support for Altera Arria10 SoCFPGA.
40 tristate "Altera FPGA Passive Serial over SPI"
43 FPGA manager driver support for Altera Arria/Cyclone/Stratix
47 tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
50 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
54 tristate "Xilinx Zynq FPGA"
57 FPGA manager driver support for Xilinx Zynq FPGAs.
63 FPGA manager driver support for Xilinx FPGA configuration
70 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
76 FPGA manager driver support for Lattice MachXO2 configuration
80 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
83 FPGA manager driver support for the Altera Cyclone II FPGA
87 tristate "FPGA Bridge Framework"
93 tristate "Altera SoCFPGA FPGA Bridges"
96 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
100 tristate "Altera FPGA Freeze Bridge"
103 Say Y to enable drivers for Altera FPGA Freeze bridges. A
104 freeze bridge is a bridge that exists in the FPGA fabric to
105 isolate one region of the FPGA from the busses while that
114 The PR Decoupler exists in the FPGA fabric to isolate one
115 region of the FPGA from the busses while that region is
119 tristate "FPGA Region"
122 FPGA Region common code. A FPGA Region controls a FPGA Manager
123 and the FPGA Bridges associated with either a reconfigurable
124 region of an FPGA or a whole FPGA.
127 tristate "FPGA Region Device Tree Overlay Support"
130 Support for loading FPGA images by applying a Device Tree
134 tristate "FPGA Device Feature List (DFL) support"
140 to provide an extensible way of adding features for FPGA.
142 devices (e.g. FPGA Management Engine, Port and Accelerator
143 Function Unit) and their private features for target FPGA devices.
146 Gate Array (FPGA) solutions which implement Device Feature List.
150 tristate "FPGA DFL FME Driver"
153 The FPGA Management Engine (FME) is a feature device implemented
156 FPGA platform level management features. There shall be one FME
157 per DFL based FPGA device.
160 tristate "FPGA DFL FME Manager Driver"
163 Say Y to enable FPGA Manager driver for FPGA Management Engine.
166 tristate "FPGA DFL FME Bridge Driver"
169 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
172 tristate "FPGA DFL FME Region Driver"
175 Say Y to enable FPGA Region driver for FPGA Management Engine.
178 tristate "FPGA DFL AFU Driver"
181 This is the driver for FPGA Accelerated Function Unit (AFU) which
183 to the FPGA infrastructure via a Port. There may be more than one
184 Port/AFU per DFL based FPGA device.
187 tristate "FPGA DFL PCIe Device Driver"
191 Field-Programmable Gate Array (FPGA) solutions which implement
194 FPGA accelerators on the FPGA DFL devices, enables system level
195 management functions such as FPGA partial reconfiguration, power
201 endif # FPGA