Lines Matching refs:FPGA
2 FPGA Device Feature List (DFL) Framework Overview
8 The Device Feature List (DFL) FPGA framework (and drivers according to this
11 configure, enumerate, open and access FPGA accelerators on platforms which
13 enables system level management functions such as FPGA reconfiguration.
20 walk through these predefined data structures to enumerate FPGA features:
21 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
52 FPGA Interface Unit (FIU) represents a standalone functional unit for the
53 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
56 Accelerated Function Unit (AFU) represents a FPGA programmable region and
71 and can be implemented in register regions of any FPGA device.
74 FIU - FME (FPGA Management Engine)
76 The FPGA Management Engine performs reconfiguration and other infrastructure
77 functions. Each FPGA device only has one FME.
92 bitstream_id indicates version of the static FPGA region.
95 bitstream_metadata includes detailed information of static FPGA region,
99 one FPGA device may have more than one port, this sysfs interface indicates
100 how many ports the FPGA device has.
105 A port represents the interface between the static FPGA fabric and a partially
107 to the accelerator and exposes features such as reset and debug. Each FPGA
129 *DFL_FPGA_PORT_RESET: reset the FPGA Port and its AFU. Userspace can do Port
151 | FPGA Container Device | Device Feature List
152 | (FPGA Base Region) | Framework
156 | FPGA DFL Device Module |
160 | FPGA Hardware Device |
164 (FPGA base region), discover feature devices and their private features from the
170 The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
177 The FPGA Management Engine (FME) driver is a platform driver which is loaded
179 provides the key features for FPGA management, including:
181 a) Expose static FPGA region information, e.g. version and metadata.
185 b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
186 bridges and FPGA regions during PR sub feature initialization. Once
188 common interface function from FPGA Region to complete the partial
191 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
207 generated for the exact static FPGA region and targeted reconfigurable region
208 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
211 the compat_id exposed by the target FPGA region. This check is usually done by
220 In the example below, two DFL based FPGA devices are installed in the host. Each
223 FPGA regions are created under /sys/class/fpga_region/
232 fpga region which represents the FPGA device.