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Searched refs:FLD_MOD (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/
Dpll.c259 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ in dss_pll_write_config_type_a()
260 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */ in dss_pll_write_config_type_a()
261 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */ in dss_pll_write_config_type_a()
263 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, in dss_pll_write_config_type_a()
266 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, in dss_pll_write_config_type_a()
272 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, in dss_pll_write_config_type_a()
275 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, in dss_pll_write_config_type_a()
287 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ in dss_pll_write_config_type_a()
291 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ in dss_pll_write_config_type_a()
293 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_a()
[all …]
Dhdmi_wp.c158 r = FLD_MOD(r, vsync_pol, 7, 7); in hdmi_wp_video_config_interface()
159 r = FLD_MOD(r, hsync_pol, 6, 6); in hdmi_wp_video_config_interface()
160 r = FLD_MOD(r, timings->interlace, 3, 3); in hdmi_wp_video_config_interface()
161 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ in hdmi_wp_video_config_interface()
217 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); in hdmi_wp_audio_config_format()
218 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); in hdmi_wp_audio_config_format()
220 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); in hdmi_wp_audio_config_format()
221 r = FLD_MOD(r, aud_fmt->type, 4, 4); in hdmi_wp_audio_config_format()
222 r = FLD_MOD(r, aud_fmt->justification, 3, 3); in hdmi_wp_audio_config_format()
223 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); in hdmi_wp_audio_config_format()
[all …]
Dhdmi4_core.c239 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); in hdmi_core_video_config()
240 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); in hdmi_core_video_config()
241 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); in hdmi_core_video_config()
242 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); in hdmi_core_video_config()
253 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); in hdmi_core_video_config()
254 r = FLD_MOD(r, 1, 5, 5); in hdmi_core_video_config()
256 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); in hdmi_core_video_config()
257 r = FLD_MOD(r, 0, 5, 5); in hdmi_core_video_config()
263 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); in hdmi_core_video_config()
264 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); in hdmi_core_video_config()
[all …]
Ddsi.c125 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
1840 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); in dsi_set_lane_config()
1841 r = FLD_MOD(r, polarity, offset + 3, offset + 3); in dsi_set_lane_config()
1848 r = FLD_MOD(r, 0, offset + 2, offset); in dsi_set_lane_config()
1849 r = FLD_MOD(r, 0, offset + 3, offset + 3); in dsi_set_lane_config()
1927 r = FLD_MOD(r, ths_prepare, 31, 24); in dsi_cio_timings()
1928 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); in dsi_cio_timings()
1929 r = FLD_MOD(r, ths_trail, 15, 8); in dsi_cio_timings()
1930 r = FLD_MOD(r, ths_exit, 7, 0); in dsi_cio_timings()
1934 r = FLD_MOD(r, tlpx_half, 20, 16); in dsi_cio_timings()
[all …]
Ddss.c70 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
277 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ in dss_sdi_init()
278 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ in dss_sdi_init()
279 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ in dss_sdi_init()
283 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ in dss_sdi_init()
284 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ in dss_sdi_init()
285 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ in dss_sdi_init()
Dhdmi5_core.c331 r = FLD_MOD(r, vsync_pol, 6, 6); in hdmi_core_video_config()
332 r = FLD_MOD(r, hsync_pol, 5, 5); in hdmi_core_video_config()
333 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); in hdmi_core_video_config()
334 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); in hdmi_core_video_config()
335 r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); in hdmi_core_video_config()
Drfbi.c71 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
331 l = FLD_MOD(l, 1, 0, 0); /* enable */ in rfbi_transfer_area()
333 l = FLD_MOD(l, 1, 4, 4); /* ITE */ in rfbi_transfer_area()
755 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ in rfbi_configure_bus()
756 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ in rfbi_configure_bus()
Ddispc.c63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
993 val = FLD_MOD(val, chan, shift, shift); in dispc_ovl_set_channel_out()
994 val = FLD_MOD(val, chan2, 31, 30); in dispc_ovl_set_channel_out()
996 val = FLD_MOD(val, channel, shift, shift); in dispc_ovl_set_channel_out()
1127 val = FLD_MOD(val, enable, 9, 9); in dispc_ovl_set_vid_color_conv()
1191 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ in dispc_init_fifos()
1192 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ in dispc_init_fifos()
1193 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ in dispc_init_fifos()
1194 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ in dispc_init_fifos()
2863 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ in dispc_wb_setup()
[all …]
Dvideo-pll.c34 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
Dhdmi5.c100 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ in hdmi_irq_handler()
101 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ in hdmi_irq_handler()
Dhdmi.h270 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
Ddss.h73 #define FLD_MOD(orig, val, start, end) \ macro
/Linux-v4.19/drivers/gpu/drm/omapdrm/dss/
Dpll.c411 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ in dss_pll_write_config_type_a()
412 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */ in dss_pll_write_config_type_a()
413 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */ in dss_pll_write_config_type_a()
415 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, in dss_pll_write_config_type_a()
418 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, in dss_pll_write_config_type_a()
424 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, in dss_pll_write_config_type_a()
427 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, in dss_pll_write_config_type_a()
439 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ in dss_pll_write_config_type_a()
443 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ in dss_pll_write_config_type_a()
445 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_a()
[all …]
Dhdmi_wp.c157 r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
158 r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */ in hdmi_wp_video_config_interface()
159 r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */ in hdmi_wp_video_config_interface()
160 r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */ in hdmi_wp_video_config_interface()
161 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3); in hdmi_wp_video_config_interface()
162 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ in hdmi_wp_video_config_interface()
237 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); in hdmi_wp_audio_config_format()
238 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); in hdmi_wp_audio_config_format()
240 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); in hdmi_wp_audio_config_format()
241 r = FLD_MOD(r, aud_fmt->type, 4, 4); in hdmi_wp_audio_config_format()
[all …]
Dhdmi4_core.c238 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); in hdmi_core_video_config()
239 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); in hdmi_core_video_config()
240 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); in hdmi_core_video_config()
241 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); in hdmi_core_video_config()
252 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); in hdmi_core_video_config()
253 r = FLD_MOD(r, 1, 5, 5); in hdmi_core_video_config()
255 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); in hdmi_core_video_config()
256 r = FLD_MOD(r, 0, 5, 5); in hdmi_core_video_config()
262 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); in hdmi_core_video_config()
263 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); in hdmi_core_video_config()
[all …]
Ddsi.c126 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
1815 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); in dsi_set_lane_config()
1816 r = FLD_MOD(r, polarity, offset + 3, offset + 3); in dsi_set_lane_config()
1823 r = FLD_MOD(r, 0, offset + 2, offset); in dsi_set_lane_config()
1824 r = FLD_MOD(r, 0, offset + 3, offset + 3); in dsi_set_lane_config()
1900 r = FLD_MOD(r, ths_prepare, 31, 24); in dsi_cio_timings()
1901 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); in dsi_cio_timings()
1902 r = FLD_MOD(r, ths_trail, 15, 8); in dsi_cio_timings()
1903 r = FLD_MOD(r, ths_exit, 7, 0); in dsi_cio_timings()
1907 r = FLD_MOD(r, tlpx_half, 20, 16); in dsi_cio_timings()
[all …]
Ddss.c70 FLD_MOD(dss_read_reg(dss, idx), val, start, end))
261 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ in dss_sdi_init()
262 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ in dss_sdi_init()
263 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ in dss_sdi_init()
267 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ in dss_sdi_init()
268 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ in dss_sdi_init()
269 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ in dss_sdi_init()
Dhdmi5_core.c340 r = FLD_MOD(r, vsync_pol, 6, 6); in hdmi_core_video_config()
341 r = FLD_MOD(r, hsync_pol, 5, 5); in hdmi_core_video_config()
342 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); in hdmi_core_video_config()
343 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); in hdmi_core_video_config()
344 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0); in hdmi_core_video_config()
Dhdmi4_cec.c226 temp = FLD_MOD(temp, 0, 4, 4); in hdmi_cec_adap_enable()
235 temp = FLD_MOD(0x0, 0x5, 2, 0); in hdmi_cec_adap_enable()
Ddispc.c66 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
1223 val = FLD_MOD(val, chan, shift, shift); in dispc_ovl_set_channel_out()
1224 val = FLD_MOD(val, chan2, 31, 30); in dispc_ovl_set_channel_out()
1226 val = FLD_MOD(val, channel, shift, shift); in dispc_ovl_set_channel_out()
1363 val = FLD_MOD(val, enable, 9, 9); in dispc_ovl_set_vid_color_conv()
1430 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ in dispc_init_fifos()
1431 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ in dispc_init_fifos()
1432 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ in dispc_init_fifos()
1433 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ in dispc_init_fifos()
2859 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ in dispc_wb_setup()
[all …]
Dvideo-pll.c34 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
Dhdmi.h288 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
Dhdmi5.c100 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ in hdmi_irq_handler()
101 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ in hdmi_irq_handler()
Ddss.h78 #define FLD_MOD(orig, val, start, end) \ macro
/Linux-v4.19/drivers/gpu/drm/gma500/
Dmdfld_dsi_output.h47 #define FLD_MOD(orig, val, start, end) \ macro
51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))