Lines Matching refs:FLD_MOD
125 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
1840 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); in dsi_set_lane_config()
1841 r = FLD_MOD(r, polarity, offset + 3, offset + 3); in dsi_set_lane_config()
1848 r = FLD_MOD(r, 0, offset + 2, offset); in dsi_set_lane_config()
1849 r = FLD_MOD(r, 0, offset + 3, offset + 3); in dsi_set_lane_config()
1927 r = FLD_MOD(r, ths_prepare, 31, 24); in dsi_cio_timings()
1928 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); in dsi_cio_timings()
1929 r = FLD_MOD(r, ths_trail, 15, 8); in dsi_cio_timings()
1930 r = FLD_MOD(r, ths_exit, 7, 0); in dsi_cio_timings()
1934 r = FLD_MOD(r, tlpx_half, 20, 16); in dsi_cio_timings()
1935 r = FLD_MOD(r, tclk_trail, 15, 8); in dsi_cio_timings()
1936 r = FLD_MOD(r, tclk_zero, 7, 0); in dsi_cio_timings()
1939 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ in dsi_cio_timings()
1940 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ in dsi_cio_timings()
1941 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ in dsi_cio_timings()
1947 r = FLD_MOD(r, tclk_prepare, 7, 0); in dsi_cio_timings()
2095 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_cio_init()
2096 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ in dsi_cio_init()
2097 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ in dsi_cio_init()
2098 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ in dsi_cio_init()
2269 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_force_tx_stop_mode_io()
2436 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ in dsi_vc_initial_config()
2437 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ in dsi_vc_initial_config()
2438 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ in dsi_vc_initial_config()
2439 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ in dsi_vc_initial_config()
2440 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ in dsi_vc_initial_config()
2441 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ in dsi_vc_initial_config()
2442 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ in dsi_vc_initial_config()
2444 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ in dsi_vc_initial_config()
2446 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ in dsi_vc_initial_config()
2447 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ in dsi_vc_initial_config()
3223 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ in dsi_set_lp_rx_timeout()
3224 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ in dsi_set_lp_rx_timeout()
3225 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ in dsi_set_lp_rx_timeout()
3226 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ in dsi_set_lp_rx_timeout()
3250 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ in dsi_set_ta_timeout()
3251 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ in dsi_set_ta_timeout()
3252 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ in dsi_set_ta_timeout()
3253 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ in dsi_set_ta_timeout()
3277 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_set_stop_state_counter()
3278 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ in dsi_set_stop_state_counter()
3279 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ in dsi_set_stop_state_counter()
3280 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ in dsi_set_stop_state_counter()
3304 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ in dsi_set_hs_tx_timeout()
3305 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ in dsi_set_hs_tx_timeout()
3306 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ in dsi_set_hs_tx_timeout()
3307 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ in dsi_set_hs_tx_timeout()
3355 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ in dsi_config_vp_sync_events()
3356 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ in dsi_config_vp_sync_events()
3357 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ in dsi_config_vp_sync_events()
3358 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ in dsi_config_vp_sync_events()
3359 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ in dsi_config_vp_sync_events()
3360 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ in dsi_config_vp_sync_events()
3361 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ in dsi_config_vp_sync_events()
3379 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ in dsi_config_blanking_modes()
3380 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ in dsi_config_blanking_modes()
3381 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ in dsi_config_blanking_modes()
3382 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ in dsi_config_blanking_modes()
3548 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); in dsi_config_cmd_mode_interleaving()
3549 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); in dsi_config_cmd_mode_interleaving()
3550 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); in dsi_config_cmd_mode_interleaving()
3554 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); in dsi_config_cmd_mode_interleaving()
3555 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); in dsi_config_cmd_mode_interleaving()
3556 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); in dsi_config_cmd_mode_interleaving()
3560 r = FLD_MOD(r, bl_interleave_hs, 31, 15); in dsi_config_cmd_mode_interleaving()
3561 r = FLD_MOD(r, bl_interleave_lp, 16, 0); in dsi_config_cmd_mode_interleaving()
3603 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ in dsi_proto_config()
3604 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ in dsi_proto_config()
3605 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ in dsi_proto_config()
3606 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ in dsi_proto_config()
3607 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ in dsi_proto_config()
3608 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ in dsi_proto_config()
3609 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ in dsi_proto_config()
3610 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ in dsi_proto_config()
3612 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ in dsi_proto_config()
3614 r = FLD_MOD(r, 0, 25, 25); in dsi_proto_config()
3678 r = FLD_MOD(r, ddr_clk_pre, 15, 8); in dsi_proto_timings()
3679 r = FLD_MOD(r, ddr_clk_post, 7, 0); in dsi_proto_timings()
3729 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ in dsi_proto_timings()
3730 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ in dsi_proto_timings()
3731 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ in dsi_proto_timings()
3735 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ in dsi_proto_timings()
3736 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ in dsi_proto_timings()
3737 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ in dsi_proto_timings()
3738 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ in dsi_proto_timings()
3742 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ in dsi_proto_timings()
3743 r = FLD_MOD(r, tl, 31, 16); /* TL */ in dsi_proto_timings()
3954 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ in dsi_update_screen_dispc()
3956 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ in dsi_update_screen_dispc()