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/Linux-v6.1/Documentation/scheduler/
D	sched-stats.rst	11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel 43 1) # of times sched_yield() was called 49 3) # of times schedule() was called 54 5) # of times try_to_wake_up() was called 55 6) # of times try_to_wake_up() was called to wake up the local cpu 78 1) # of times in this domain load_balance() was called when the 79 cpu was idle 81 the load did not require balancing when the cpu was idle 83 more tasks and failed, when the cpu was idle 85 load_balance() in this domain when the cpu was idle [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	41 "BriefDescription": "Cycles when a demand ifetch was pending", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … [all …]
D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f… 30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 … [all …]
D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local… [all …]
D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum… 30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu… 36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch… 42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi… 59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,… 60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p… 65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an… [all …]
D	marked.json	35 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 47 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 107 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 119 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch co… 131 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp… 143 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict… 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … [all …]
D	translation.json	29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… 77 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 83 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power9/
D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i… 50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
D	frontend.json	5 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 15 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 25 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in… 40 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 50 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 55 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict… 70 …"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in th… 85 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from… 95 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
D	translation.json	15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor… 25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 75 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same… 115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t… [all …]
D	pipeline.json	25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… [all …]
D	cache.json	35 …ause the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this lo… 40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 90 …ription": "Finish stall because the NTF instruction was a load that hit on an older store and it w… 100 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 105 … "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power10/
D	frontend.json	25 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling… 30 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 40 …n which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR … 45 …"BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access)… 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L… 95 …"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT… 100 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 105 "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss." 110 …"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held… [all …]
D	metrics.json	16 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled for any re… 22 …ion": "Average cycles per completed instruction when dispatch was stalled because there was a flus… 28 …on": "Average cycles per completed instruction when dispatch was stalled because the MMU was handl… 34 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to… 40 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to… 46 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an … 52 …: "Average cycles per completed instruction when dispatch was stalled while the instruction was fe… 58 …: "Average cycles per completed instruction when dispatch was stalled while the instruction was fe… 64 …: "Average cycles per completed instruction when dispatch was stalled while the instruction was fe… 70 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an … [all …]
/Linux-v6.1/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	10 Soon after the V4L API was added to the kernel it was criticised as too 15 another four years and two stable kernel releases until the new API was 23 1998-08-27: The :c:func:`select()` function was introduced. 27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise 39 1998-10-02: The ``id`` field was removed from 41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was 45 Codec API was released. 50 1998-11-12: The read/write directon of some ioctls was misdefined. 57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from 58 ``videodev.h`` since it was only used once in the ``videodev`` kernel [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z14/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …on Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for… 21 …s for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DT… 28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a … 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement… 56 …r the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the IT… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z15/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …on Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for… 21 …s for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DT… 28 …"PublicDescription": "A translation entry was written into the Combined Region and Segment Table E… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement… 56 …r the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the IT… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… [all …]
/Linux-v6.1/arch/arm/tools/
D	syscall.tbl	`21 # 7 was sys_waitpid 31 # 17 was sys_break 32 # 18 was sys_stat 42 # 28 was sys_fstat 45 # 31 was sys_stty 46 # 32 was sys_gtty 49 # 35 was sys_ftime 58 # 44 was sys_prof 62 # 48 was sys_signal 67 # 53 was sys_lock [all …]`
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …ookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement… 21 …s for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DT… 28 …"PublicDescription": "A translation entry was written into the Combined Region and Segment Table E… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement… 49 …r the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the IT… 56 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… 98 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the re… 105 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the re… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z13/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 133 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 140 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 147 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 154 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
D	ifu.json	45 …"PublicDescription": "A 2nd instruction could have been pushed but was not because it was nonseque… 48 …"BriefDescription": "A 2nd instruction could have been pushed but was not because it was nonsequen… 75 …"PublicDescription": "This thread was arbitrated when the other thread was also ready for scheduli… 78 …"BriefDescription": "This thread was arbitrated when the other thread was also ready for schedulin… 81 …"PublicDescription": "This thread was arbitrated when the other thread was also active, but not ne… 84 …"BriefDescription": "This thread was arbitrated when the other thread was also active, but not nec… 87 …"PublicDescription": "This thread was not arbitrated because it was not ready for scheduling. For … 90 …"BriefDescription": "This thread was not arbitrated because it was not ready for scheduling. For e…
/Linux-v6.1/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	21 …ritebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 221 …ad uops retired that hit in the L3 cache, in which a snoop was required and modified data was forw… 391 …ads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 402 … reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 413 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … 424 …": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop … 435 …: "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy t… 468 …hes that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 479 …etches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 490 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	21 …ritebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 221 …ad uops retired that hit in the L3 cache, in which a snoop was required and modified data was forw… 391 …ads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 402 … reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 413 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … 424 …": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop … 435 …: "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy t… 468 …hes that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 479 …etches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 490 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_zec12/
D	extended.json	21 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 28 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 35 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …A directory write to the Level-1 Data cache where the installed cache line was sourced from memory… 56 …tory write to the Level-1 Instruction cache where the installed cache line was sourced from memory… 63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in… 105 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … [all …]

12 3 4 5 6 7 8 9 10 >>...108