Lines Matching full:was
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch…
180 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
185 …"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's …
190 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
195 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
225 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl…
235 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
245 …"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the cor…
250 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
260 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
265 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
270 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
275 …"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating P…
285 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
310 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
325 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
350 …"BriefDescription": "The processor's Instruction cache was reloaded from a memory location includi…
380 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
390 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
395 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
400 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
435 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
440 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
450 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a mark…
460 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a …
480 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp…
485 "BriefDescription": "Cycles L3 miss was pending for this thread"
490 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L…
495 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru…
515 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
525 …": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full"