| /Linux-v6.1/drivers/clk/versatile/ |
| D | clk-icst.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
37 * struct clk_icst - ICST VCO clock wrapper
40 * @vcoreg_off: VCO register address
41 * @lockreg_off: VCO lock register address
59 * vco_get() - get ICST VCO settings from a certain ICST
61 * @vco: the VCO struct to return the value in
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| D | clk-icst.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * enum icst_control_type - the type of ICST control register
18 * struct clk_icst_desc - descriptor for the ICST VCO
20 * @vco_offset: offset to the ICST VCO from the provided memory base
21 * @lock_offset: offset to the ICST VCO locking register from the provided
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
38 integratorap-cm
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| D | st,stm32-rcc.txt | 6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
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| /Linux-v6.1/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
27 /* number of VCO frequency bands */
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
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| D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
62 * auto calculates VCO frequency parameters based on the provided leaf
79 * Parameters for VCO frequency configuration
81 * VCO frequency =
92 unsigned int offset; member
101 unsigned int offset; member
111 unsigned int offset; member
121 unsigned int offset; member
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| /Linux-v6.1/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | arm-realview-eb.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-eb";
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
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| D | arm-realview-pb11mp.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
60 next-level-cache = <&L2>;
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| D | integratorap.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "arm,integrator-ap";
16 #address-cells = <1>;
17 #size-cells = <0>;
27 /* compatible = "arm,arm926ej-s"; */
30 * The documentation in ARM DUI 0138E page 3-12 states
32 * but painful trial-and-error has proved to me that it
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| D | arm-realview-pbx.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-pbx";
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
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| D | arm-realview-pb1176.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb1176";
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
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| D | integratorcp.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
51 #clock-cells = <0>;
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| /Linux-v6.1/drivers/media/tuners/ |
| D | max2165.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
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| /Linux-v6.1/drivers/clk/tegra/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
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| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | radeon_uvd.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
74 switch (rdev->family) { in radeon_uvd_init()
134 return -EINVAL; in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init()
143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init()
149 r = radeon_ucode_validate(rdev->uvd_fw); in radeon_uvd_init()
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | clk-alpha-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
56 #define VCO(a, b, c) { \ macro
63 * struct clk_alpha_pll - phase locked loop (PLL)
64 * @offset: base address of registers
65 * @vco_table: array of VCO settings
70 u32 offset; member
85 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
86 * @offset: base address of registers
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| D | clk-cpu-8996.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * +-------+
14 * +------------------>0 |
16 * PLL/2 | SMUX +----+
17 * +------->1 | |
19 * | +-------+ | +-------+
20 * | +---->0 |
22 * +---------------+ | +----------->1 | CPU clk
23 * |Primary PLL +----+ PLL_EARLY | | +------>
24 * | +------+-----------+ +------>2 PMUX |
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| /Linux-v6.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
98 int offset, int data) in hdmi_tx_chan_write() argument
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
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| /Linux-v6.1/drivers/media/dvb-frontends/ |
| D | stb6100.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
162 dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg); in stb6100_read_reg()
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| /Linux-v6.1/drivers/media/i2c/ |
| D | mt9t112.c | 1 // SPDX-License-Identifier: GPL-2.0
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
20 * v4l-utils compliance tools will report errors.
30 #include <linux/v4l2-mediabus.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
76 #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) argument
77 #define VAR(id, offset) _VAR(id, offset, 0x0000) argument
78 #define VAR8(id, offset) _VAR(id, offset, 0x8000) argument
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| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 2 * Copyright © 2006-2017 Intel Corporation
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
107 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
113 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
119 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
125 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
131 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
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| /Linux-v6.1/drivers/clk/ |
| D | clk-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by clk-asm9260.c .
8 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/stm32fx-clock.h>
42 #define NONE -1
48 u8 offset; member
403 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
472 return ERR_PTR(-ENOMEM); in clk_register_apb_mul()
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| /Linux-v6.1/include/video/ |
| D | w100fb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 2004-2005 Richard Purdie
58 unsigned long offset; member
95 uint8_t N_int; /* VCO multiplier */
96 uint8_t N_fac; /* VCO multiplier fractional part */
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| /Linux-v6.1/drivers/gpu/drm/gma500/ |
| D | gma_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
30 struct drm_device *dev = crtc->dev; in gma_pipe_has_type()
36 if (connector->encoder && connector->encoder->crtc == crtc) { in gma_pipe_has_type()
39 if (gma_encoder->type == type) { in gma_pipe_has_type()
59 struct drm_device *dev = crtc->dev; in gma_pipe_set_base()
62 struct drm_framebuffer *fb = crtc->primary->fb; in gma_pipe_set_base()
64 int pipe = gma_crtc->pipe; in gma_pipe_set_base()
65 const struct psb_offset *map = &dev_priv->regmap[pipe]; in gma_pipe_set_base()
66 unsigned long start, offset; in gma_pipe_set_base() local
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