Searched +full:usb3 +full:- +full:phy0 (Results 1 – 19 of 19) sorted by relevance
/Linux-v5.10/Documentation/devicetree/bindings/usb/ |
D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Neil Armstrong <narmstrong@baylibre.com> 14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode 18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY. 20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP. 26 host-only mode. [all …]
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/Linux-v5.10/arch/arm64/boot/dts/amlogic/ |
D | meson-g12b-a311d-khadas-vim3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 /dts-v1/; 10 #include "meson-g12b-a311d.dtsi" 11 #include "meson-khadas-vim3.dtsi" 12 #include "meson-g12b-khadas-vim3.dtsi" 19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 21 * an USB3.0 Type A connector and a M.2 Key M slot. 23 * the USB3.0 controller and the PCIe Controller, thus only 25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines 27 * USB3.0 from the USB Complex and enable the PCIe controller. [all …]
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D | meson-g12b-s922x-khadas-vim3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 /dts-v1/; 10 #include "meson-g12b-s922x.dtsi" 11 #include "meson-khadas-vim3.dtsi" 12 #include "meson-g12b-khadas-vim3.dtsi" 19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 21 * an USB3.0 Type A connector and a M.2 Key M slot. 23 * the USB3.0 controller and the PCIe Controller, thus only 25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines 27 * USB3.0 from the USB Complex and enable the PCIe controller. [all …]
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D | meson-sm1-khadas-vim3l.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include "meson-sm1.dtsi" 10 #include "meson-khadas-vim3.dtsi" 11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h> 17 vddcpu: regulator-vddcpu { 21 compatible = "pwm-regulator"; 23 regulator-name = "VDDCPU"; 24 regulator-min-microvolt = <690000>; 25 regulator-max-microvolt = <1050000>; [all …]
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D | meson-g12-common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/phy/phy.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/clock/g12a-clkc.h> 9 #include <dt-bindings/clock/g12a-aoclkc.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; [all …]
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/Linux-v5.10/arch/arm64/boot/dts/marvell/ |
D | armada-3720-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (DB-88F3720-DDR3) 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 14 /dts-v1/; 16 #include <dt-bindings/gpio/gpio.h> 17 #include "armada-372x.dtsi" 20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; 21 compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; 24 stdout-path = "serial0:115200n8"; 32 exp_usb3_vbus: usb3-vbus { [all …]
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D | armada-7040-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/gpio/gpio.h> 9 #include "armada-7040.dtsi" 13 compatible = "marvell,armada7040-db", "marvell,armada7040", 14 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 17 stdout-path = "serial0:115200n8"; 31 cp0_exp_usb3_0_current_regulator: gpio-regulator { 32 compatible = "regulator-gpio"; 33 regulator-name = "cp0-usb3-0-current-regulator"; 34 regulator-type = "current"; [all …]
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D | armada-8040-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/gpio/gpio.h> 9 #include "armada-8040.dtsi" 13 compatible = "marvell,armada8040-db", "marvell,armada8040", 14 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 17 stdout-path = "serial0:115200n8"; 34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 35 compatible = "regulator-fixed"; 36 regulator-name = "cp0-usb3h0-vbus"; 37 regulator-min-microvolt = <5000000>; [all …]
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/Linux-v5.10/arch/arm/boot/dts/ |
D | armada-385-synology-ds116.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 /dts-v1/; 9 #include "armada-385.dtsi" 10 #include <dt-bindings/gpio/gpio.h> 14 compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; 17 stdout-path = "serial0:115200n8"; 32 internal-regs { 34 pinctrl-names = "default"; 35 pinctrl-0 = <&i2c0_pins>; 37 clock-frequency = <100000>; [all …]
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D | armada-388-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (DB-88F6820) 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 /dts-v1/; 12 #include "armada-388.dtsi" 16 compatible = "marvell,a385-db", "marvell,armada388", 20 stdout-path = "serial0:115200n8"; 35 internal-regs { 38 clock-frequency = <100000>; 43 clock-frequency = <100000>; [all …]
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D | armada-388-rd.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (RD-88F6820-AP) 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 /dts-v1/; 13 #include "armada-388.dtsi" 17 compatible = "marvell,a385-rd", "marvell,armada388", 21 stdout-path = "serial0:115200n8"; 35 internal-regs { 38 clock-frequency = <100000>; [all …]
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D | armada-388-gp.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 * (RD-88F6820-GP) 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 11 /dts-v1/; 12 #include "armada-388.dtsi" 13 #include <dt-bindings/gpio/gpio.h> 16 model = "Marvell Armada 388 DB-88F6820-GP"; 17 compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; 20 stdout-path = "serial0:115200n8"; 35 internal-regs { [all …]
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D | armada-388-helios4.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 10 /dts-v1/; 11 #include "armada-388.dtsi" 12 #include "armada-38x-solidrun-microsom.dtsi" 25 /* So that mvebu u-boot can update the MAC addresses */ 30 stdout-path = "serial0:115200n8"; 33 reg_12v: regulator-12v { 34 compatible = "regulator-fixed"; 35 regulator-name = "power_brick_12V"; 36 regulator-min-microvolt = <12000000>; [all …]
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D | armada-385-db-ap.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 * (DB-88F6820-AP) 11 /dts-v1/; 12 #include "armada-385.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; 21 stdout-path = "serial1:115200n8"; 36 internal-regs { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&i2c0_pins>; [all …]
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D | armada-370-dlink-dns327l.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree file for D-Link DNS-327L 12 /dts-v1/; 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include "armada-370.dtsi" 19 model = "D-Link DNS-327L"; 22 "marvell,armada-370-xp"; 25 stdout-path = &uart0; 38 internal-regs { [all …]
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/Linux-v5.10/drivers/reset/ |
D | reset-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 13 #include <linux/reset-controller.h> 23 #define UNIPHIER_RESET_ID_END (unsigned int)(-1) 54 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */ 59 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */ 67 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */ 81 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ 82 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ 83 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ 84 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/phy/ |
D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes" 5 - reg : Address and length of the register set for the device. 6 - #phy-cells: determine the number of cells that should be given in the 9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes 12 0 - USB3 13 1 - PCIe0 Lane0 14 2 - ICSS2 SGMII Lane0 16 0 - PCIe1 Lane0 17 1 - PCIe0 Lane1 18 2 - ICSS2 SGMII Lane1 [all …]
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/Linux-v5.10/drivers/usb/dwc3/ |
D | dwc3-meson-g12a.c | 1 // SPDX-License-Identifier: GPL-2.0 11 * - Control registers for each USB2 Ports 12 * - Control registers for the USB PHY layer 13 * - SuperSpeed PHY can be enabled only if port is used 14 * - Dynamic OTG switching with ID change interrupt 33 /* USB2 Ports Control Registers, offsets are per-port */ 120 "usb2-phy0", "usb2-phy1", "usb2-phy2", 124 "usb2-phy0", "usb2-phy1", "usb3-phy0", 133 * correctly when only the "usb2-phy1" phy is specified on-par with the 137 "usb2-phy0", "usb2-phy1" [all …]
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/Linux-v5.10/arch/arm64/boot/dts/ti/ |
D | k3-j721e-common-proc-board.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 6 /dts-v1/; 8 #include "k3-j721e-som-p0.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/net/ti-dp83867.h> 15 stdout-path = "serial2:115200n8"; 19 gpio_keys: gpio-keys { 20 compatible = "gpio-keys"; [all …]
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